March 1999, Issue 104

JTAG—Working with CoolPLD

DESIGN TOOLS

Philips has a full line of tools starting with a $99 Coolrunner XPLA designer kit. To simplify the hardware side, a $50 ISP prototype board lets you see some immediate results. The ISP board comes with a PLCC PZ5128 CPLD device, a two-digit seven-segment LCD, and lots of prototyping area.

The XPLA designer software is a Windows-based suite of tools that carries you through the five steps of a CPLD design—design definition, device fitting, functional simulation, timing simulation, and programming. The XPLA designer produces a jedec output file that the ISP prototyping board and programming software use to program a device through the JTAG port.

The process begins with the design definition. XPLA designer uses a hardware descriptive language (HDL) for design entry. This HDL is supported in one of three formats—Boolean equations, state machines, and truth tables.

A Philips hardware design text file (.PHD) is created to hold the design definition. This file contains three basic sections—the header, declarations, and logic description. The header is information (e.g., title and special notes of interest) about the design.

The declaration section is where all of the I/O pins and internal nodes are defined and the constants, variables, and macro functions are declared. A macro is a reusable predefined function such as an octal latch, which is made up of eight individual latches with the appropriate control logic. Because this device may be used multiple times in the same CPLD design or in future designs, it makes sense to save it as a macro function.

Naturally, it takes time to learn all the shortcuts. The most important concept here is that every net of the design must be identified for the compiler to see the whole picture.

The logic description holds all the equation information on how the output signals respond to various input signals. Equations can be entered in Boolean format (e.g., a simple two-input AND gate where ANDOUT = ANDIN1 & ANDIN2). Listing 2 shows the truth-table format for the same gate.

truth_table
([ANDIN1,ANDIN2]->[ANDOUT])
	[0,0]->[0];
	[0,1]->[0];
	[1,0]->[0];
	[1,1]->[1];

The last equation format is that of the state machine. This registered equation uses a clock for state transitions. The equation to determine direction of a biphase optical encoder might follow the form shown in Listing 1.