March
1999, Issue 104
JTAG—Working
with CoolPLD
XPLA
ARCHITECTURE
The
PZ3065 and PZ5064 (3 and 5 V, respectively) are the
smallest CPLDs that Philips manufactures with the JTAG
ISP. They are packaged in various package sizes and
styles from 44-pin PLCC to 100-pin QFP.
The
packages with more pins offer more I/O without necessarily
increasing the macrocell count. If you need more facilities,
the larger pin packages let you substitute a higher
density CPLD without having to redesign the board.
The
XPLA architecture is made up of multiple logic blocks
(LBs), which are interconnected by a zero-power interconnect
array (ZIA). The ZIA is a large row/column array consisting
of inputs to each LB and feedback from each macrocell
and I/O pin (see Figure 1).
|
Figure 1—The
XPLA architecture shows how the logic block and
macrocells are interconnected using a cross point
switch (ZIA).
|
Figure
2 shows the PAL array of 16 individually programmable
five-input AND gates (built for speed) that make up
each LB. Each gate is OR’d into one of 16 macrocells
along with a programmable PLA array of 32 AND/OR gates
used when there’s a need for increased product
term density. The ZIA also supplies six possible control
terms in support of the macrocells.
|
Figure 2—The
logic block section consists of PAL and PLA arrays,
providing a combination of speed and increased
product term density.
|
Each
macrocell consists of a flip-flop that is configurable
for either D or T types (see Figure 3). The clock to
the flip-flop can be synchronous or asynchronous and
can clock off either the rising or falling edge.
|
Figure 3—The
macrocell has a variety of clocking options as
well as feedback before and after the I/O buffer.
|
Up
to four different clocks are available to the macrocells.
They can be from synchronous external sources or asynchronous
internal macrocell outputs. Powerup initializes all
F/Fs into an initial 0 state, but preset and reset inputs
can be implemented using two of the four control lines
from the ZIA.
The
remaining four control terms can be selected as output-enable
control. Notice that the macrocell can be bypassed if
necessary. Also, all outputs have a global tristate
(*GTS) control.
GTS
control, when enabled, permits all the pins on the device
to be tristated by a single input pin. This arrangement
releases the driving potential of all outputs to aid
in testing (which could also be accomplished via the
JTAG facilities).
Feedback
to the ZIA comes from the macrocells’ output and
the I/O pin, with the output driver between the two.
When the pin is used as an output, it’s driven
from the macrocell (via its output driver) or the ZIA.
When
the pin is used as an input, the macrocell’s output
driver is disabled. The input then goes to the ZIA,
and the macrocell’s output is also fed back to
the ZIA.
