March
1999, Issue 104
JTAG—Working
with CoolPLD
ISP,
JTAG STYLE
Somewhere
along the development path, programmable-logic manufacturers
started eyeing the flexibility of the JTAG testability
standard. JTAG architecture enabled these manufacturers
to solve the in-circuit programming problem by simply
adding additional programming logic and allowing control
via JTAG extensions.
By
increasing the instruction register size (bit width),
you allow additional programming instructions. These
instructions enable an additional data register called
the ISP register.
The
ISP register is how the programming information actually
gets to the array fuses (E2). Voilą—in-circuit
programming via the JTAG port.
Philips
Semiconductor is one manufacturer of CPLDs. They have
a family of fast (almost) zero-power (FZP) devices with
JTAG ISP in 3- and 5-V versions.
These
FZP devices use extended programmable-logic arrays (XPLA)
to achieve macrocell propagations in the low nanoseconds
while keeping currents in the low milliamperes at speeds
above 1 MHz. Figure 1 gives you an idea of how the XPLA
is laid out.
