SPI-FI

Let’s turn our attention to the other side of the chip for a moment. Here you find the familiar SPI that delivers the digital goods up the chain of command. And here you also find a problem—namely, so many bits, so little time, and so few pins.

I just finished saying that the ADC can run at up to 75 MHz, delivering 16 bits of data each clock. Excuse me, but last time I looked, there weren’t many chips out there with a 1.2-GHz SPI! As a practical matter, the feasible sample rate is dictated by the chip’s maximum SPI clock rate, which is 40 MHz. You can get up to 2.5 Msps in Single Channel mode, which outputs 16-bit words. But, as you can see in Table 2, adding channels cuts the maximum sample rate, more so because 24 bits are output for each sample in Multi-Channel mode (see Figure 2).

There’s another seemingly odd thing about the interface. The good news is that the over-sampling ratio can be set independently to optimize the speed/resolution (ENOB) trade-off for each channel. The data rate out the SPI port is dictated by the channel configured for the highest real sample rate. But data is output from every active channel at the high-speed channel’s rate, even data from channels running at a lower speed (i.e. higher over-sampling ratio). That means data from lower-speed channels is output at an artificially high rate with dummy outputs (previous data with new data flag not set) possibly outnumbering real ones (new data and new data flag set).