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March 2000, Issue 116

Building a RISC System In AN FPGA Part 1:
Tools, Instruction, Set and Datapath


by Jan Gray

To kick off this three-part article, Jan’s going to port a C compiler, design an instruction set, write an assembler and simulator, and design the CPU datapath. Get reading, you’ve only got a month before your connecting article arrives.


Start The Project C Compiler Instruction Set Assembler FPGA The Processor Interface Datapath Resources Datapath Schematic Register File Operand Selection ALU Result Mulitplexer Address/PC Unit The Datapath In Action Development Tools High Performance Design References, Sources & PDF

I used to envy CPU designers—the lucky engineers with access to expensive tools and fabs. But, field-programmable gate arrays (FPGAs) have made custom-processor and integrated-system design much more accessible.

20–50-MHz FPGA CPUs are perfect for many embedded applications. They can support custom instructions and function units, and can be reconfigured to enhance system-on-chip (SoC) development, testing, debugging, and tuning. Of course, FPGA systems offer high integration, short time-to-market, low NRE costs, and easy field updates of entire systems.

FPGA CPUs may also provide new answers to old problems. Consider one system designed by Philip Freidin. During self-test, its FPGA is configured as a CPU and it runs the tests. Later the FPGA is reconfigured for normal operation as a hardwired signal processing datapath. The ephemeral CPU is free and saves money by eliminating test interfaces.