THE PROCESSOR INTERFACE

Figure 1 gives you a good look at the xr16 processor macro symbol. The interface was designed to be easy to use with an on-chip bus. The key signals are the system clock (CLK), next memory address (AN15:0), next access is a read (READN), next access is 16-bit data (WORDN), address clock enable: above signals are valid, start next access (ACE), memory ready input: the current access completes this cycle (RDY), instruction word input (INSN15:0), on-chip bidirectional data bus to load/store data (D15:0).

Figure 1—The xr16 processing symbol ports, which include instruction and data buses, next address and memory controls, and bus controls, constitute its interface to the system memory controller.

The memory/bus controller (which I’ll explain further in Part 3) decodes the address and activates the selected memory or peripheral. Later it asserts RDY to signal that the memory access is done.

As Figure 2 shows, the CPU is simply a datapath that is steered by a control unit. Next month, I’ll examine the control unit in greater detail. The rest of this article explores the design and implementation of the datapath.

Figure 2—The control unit receives instructions, decodes them, and drives both the memory control outputs and the datapath control signals.