HIGH PERFORMANCE DESIGN

The datapath implementation showcases some good practices, such as exploiting FPGA features (using embedded SRAM, four input logic structures, TBUFs, and flip-flop clock enables), floorplanning (placing functions in columns, ordering columns to reduce interconnect requirements, and running the 3-state bus horizontally over the columns), iterative design (measuring the area and delay effects of each potential feature), and using timing-driven place-and-route and iterative timing improvement.

I apply timing constraints, such as net CLK period=28;, which causes par to find critical paths in the design and prioritize their placement and routing to best meet the constraints. Next, I run trce to find critical paths. Then I fix them, rebuild, and repeat until performance is satisfactory.

I’ve built some tools, settled on an instruction set, built a datapath to execute it, and learned how to implement it efficiently in an FPGA. Next month, I’ll design the control unit. ?

Jan Gray is a software developer whose products include a leading C++ compiler. He has been building FPGA processors and systems since 1994, and now he designs for Gray Research LLC. You may reach him at jan@fpgacpu.org.