DEVELOPMENT TOOLS

This hardware was designed, simulated, and compiled on a PC using the Foundation tools in Xilinx Student Edition 1.5. I used schematics for this project because their 2-D layout makes it easier to understand the data flow because they offer explicit control and because they support the RLOC (relative location) placement attributes that are essential to floorplanning (to achieve the smallest, fastest, cheapest design).

To compile my schematics into a configuration bitstream, Foundation runs these tools:

• map: technology mapping—map schematic’s arbitrary logic structures into the device’s LUTs and flip-flops
• par: place and route—place the logic and flip-flops in specific CLBs and then route signals through the programmable interconnect
• trce: static timing analysis—enumerate all possible signal paths in the design and report the slowest ones
• bitgen: generate a bit stream configuration file for the design