THE DATAPATH IN ACTION

Next, let’s see what happens when we run 0008: addi r3,r1,2. Assuming that PC=6 and r1=10, PCINCR adds PCDISP=2 to PC=6, giving PCNEXT=8. Because SELPC is true, ADDR ? PCNEXT=8, and the next memory cycle reads the word at 0008. Because PCCE is true, PC is updated to 8.

Some time later, RDY is asserted and the control unit latches 0x2312 (addi r3,r1,2) into its instruction register. The control unit sets RNA=1, so AREG=r1. BREG is not used. FWD is false so A=AREG=r1=10. IMMOP is set to sign-extend the 4-bit imm field, and so B=2.

We add A+B=10+2 and as SUMT is asserted (low), we drive SUM=12 onto the RESULT bus. The control unit asserts RFWE (register file write enable), and sets RNA=RNB=3 to write the result into both REGFILEs’ r3.