ADDRESS/PC UNIT

This unit generates memory addresses for instruction fetch, load/store, and DMA memory accesses. For each cycle, we add PC += 2 to fetch the next instruction. For a taken branch, we add PC += 2?disp8. For jal and call, we load PC with the effective address SUM from ADDSUB.

Refer to Figure 3 to see how this arrangement works. PCINCR adds PC and the PCDISP mux output (either +2 or the branch displacement) giving PCNEXT. ADDRMUX then selects PCNEXT or SUM as the next memory address.

If the next memory access is an instruction fetch, ADDR ? PCNEXT, and PCCE (PC clock enable) is asserted to update PC with PCNEXT. When the next access is a load/store, SELPC and PCCE are false, and ADDR ? SUM, without updating PC.

PCDISP is a 16-bit mux of +215:0 and 2×disp8, 5 CLBs tall. PCINCR is an instance of the ADD16 library symbol, 9 CLBs tall. ADDRMUX is a 16-bit 2-1 mux with a fourth input, ZERO, to set PC to 0 on reset. It’s 16 LUTs, 8 CLBs tall.

PC is not a simple register, but rather it is a 16-entry register file. PC0 is the CPU PC, and PC1 is the DMA address. PC is a 16 × 16 RAM, eight CLBs tall.

I used RLOC attributes to place the datapath elements. Figure 4 is the resulting floorplan on the 14 × 14 CLB FPGA. Each column of CLBs provides logic, flip-flops, and TBUF resources.

Figure 4—In the datapath floorplan, RLOC attributes applied to the datapath schematic pin down the datapath elements to specific CLB locations. The RESULT15:0 bus runs horizontally across the bottom eight rows of CLBs.