RESULT MULTIPLEXER

The result mux selects the instruction result from the adder, logic unit, A>>1, A<<1, load data, or return address. You build this 16-bit 7-1 mux from lots of 3-state buffers (TBUFs). In every cycle, the control unit asserts some resource’s output enable, driving its output onto the RESULT15:0 long line bus that spans the FPGA.

In the third article of this series, I’ll share the CPU result bus as the 16-bit on-chip data bus for load/store data. During sw or sb, the CPU drives DOUT7:0 and/or DOUT15:8 onto RESULT15:0. During lw or lb, the selected memory or peripheral drives the load data on RESULT15:0 or RESULT7:0.