OPERAND SELECTION

With the two source registers AREG and BREG in hand, you now select the A and B operands, and latch them in the A and B registers. Some examples are shown in Table 5.

The A operand is AREG unless (as with add2) the instruction depends on the result of the previous instruction. Next month, you’ll see why this pipeline data hazard is avoided by forwarding the add1 result directly into the A register, just in time for add2.

FWD, a 16-bit mux of AREG or RESULT, does this result forwarding. It consists of 16 1-bit muxes, each a 3-input function implemented in a single 4-LUT, and arranged in a column of eight CLBs. The FWD output is captured in the A operand register, made from the 16 flip-flops in the same CLBs. As for the B operand, select either the BREG register file output port or an immediate constant.

For rri and ri format instructions, B is the zero- or sign-extended 4-bit imm field of the instruction register. But, if there’s an imm prefix, load B15:4 with its 12-bit imm12 field, then load B3:0 while decoding the rri or ri format instruction which follows.

So, the B operand mux IMMED is a 16-bit-wide selection of either BREG, 015:4||IR3:0, sign15:4||IR3:0, or IR11:0||03:0 ("||" means bit concatenation).

I used an unusual 2-1 mux with a fourth "force constant" input for this zero/sign extension function, primarily because it fits in a single 4-LUT. So, as with FWD, IMMED is an 8-CLB column of muxes.

The B operand register uses IMMED’s CLBs 16 flip-flops. The register has separate clock enables for B15:4 and B3:0, to permit separate loading of the upper and lower bits for an imm prefix.

For sw or sb, read the register to be stored, via BREG, into DOUT15:0, another column of eight CLBs flip-flops.