February 1998, Issue 91

Codesign
The Evolving Relationship Between Hardware and Software

On the simulation front, Mentor Graphics recently released its Seamless Co-Verification Environment (CVE). Using a unique approach to speeding up the verification process, this system enables the designer to minimize the time spent in logic simulation by isolating the CPU and memory from the rest of the system logic.

The CPU is modeled using an instruction-set simulator (ISS), which can run compiled C or assembly code at millions of instructions per second in full-emulation mode. The ISS tracks the number of CPU cycles required for each operation for performance analysis and synchronizing with the rest of the system. By abstracting the memory in addition to the CPU, a majority of the bus cycles, which are simply data or instruction fetches, can be avoided.

To handle concerns about accuracy or analysis at a deeper level, a bus functional model is also created in C to enable the logic simulator to stimulate bus activity and interact with the rest of the system logic. The memory system is also modeled in the logic simulator so it’s visible to the rest of the logic. The memory and bus functional models communicate with the ISS using an API.

However, this approach alone is not enough, since waiting for the logic simulator to complete each operation renders it unusable. In addition, the contents of the memory model in the simulator must synchronize with the image expected by the CPU without tying up resource-intensive bus cycles.

To solve this problem, Seamless CVE employs an intelligent kernel between the ISS and logic simulator. It keeps the two simulations synchronized and maintains a consistent view of memory for the CPU and logic.

Most importantly, it optimizes the performance of the overall system simulation by letting the user selectively filter certain classes of bus activity to avoid unnecessary stimulation of the logic simulator. For example, once the instruction fetch cycle has been characterized for a portion of the memory map, fetches can be turned off to reduce load on the logic simulator.

The main disadvantage to the simulation approach is that it requires the development of a number of critical models—an ISS model for the target processor and any off-the-shelf VLSI components, a bus-functional model, and a memory model.

If models are not readily available from the chip vendor in a form that works with Seamless CVE, the time required to create them can add months to the overall development cycle. Plus, most vendors won’t provide them even if they are available unless a binding nondisclosure agreement is signed and you’re signed up to buy chips. Some vendors refuse to supply these models or even develop them to protect their intellectual property.

You can also include actual components in your virtual prototype if they’re available, or you can do hardware emulation of blocks using Mentor’s SimExpress box. Mentor’s strategy is to enable designers to create the level of abstraction required.

Both approaches require hardware to be well-modeled and -defined before the creation of the virtual prototype, much more so than the software. The software then turns up bugs that require a redesign on portions of the hardware.