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HARDWARE

The first stage in our circuit is the output stage, where the 125-kHz signal is created, amplified, and transmitted over the antenna (see Figure 2). In order to better understand motivations for the creation and amplification parts of this stage, it is probably best to start with the last (but probably most crucial) part of the stage: the resonant antenna LC circuit.

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Figure 2—Take a look at the complete reader circuit. Start at the top right and move clockwise to follow the circuit as it manipulates the signal into useable data.

There are typically two ways to design an LC antenna: putting the inductor and capacitor in series or in parallel. Both serve their purpose well; however, when reading Microchip technology's extremely helpful “microID 125-kHz RFID System Design Guide,” we learned that we should go for the series implementation. With a series-resonant circuit, you get maximum admittance (highest current) at the resonant frequency.

To choose the values for our inductive antenna and capacitor, we used:

where f0 is our resonant frequency (125 kHz). For our particular design, we had a lot of 1-nF capacitors around the lab, so we designed around this. Doing so gave us a target inductance of 1.62 mH. We wound the antenna out of lacquered copper wire in a rectangular configuration. This enabled us to incorporate the antenna in our “housing” and still keep it fairly compact.

The loop’s inductance is:

L is in microhenries. x and y are the width and length of the coil (in centimeters). h is the height of the coil (in centimeters). b is the width across the conducting part of the coil (in centimeters). N is the number of turns. In our case, x was 3.6 cm and y was 13.8 cm. We estimated that h was 1 cm and b was 0.3 cm. Using the equation, we calculated that the coil needed approximately 90 turns. We tuned the coil afterwards to achieve maximum resonance on a 125-kHz signal, which is important for getting higher read distances.

The next big step in the design was actually generating the carrier signal. For this we used one of the three timers found on the ATmega32. We were using a 16-MHz clock, so the 125 kHz is a straight division of that. As a result, all we had to do was initialize the timer with that prescalar and set the TIMSK register to output that from its respective output pin. We then put the square wave through an RF choke (basically a beefy low-pass filter) in order to remove all the extra harmonics created by the square wave. This produced a 125-kHz sine wave. Note that at maximum resonance we have extremely high current, so we have to amplify this signal lest we blow out the ATmega32.

For the amplifier we used a PNP emitter-follower stage followed by a BJT Half-bridge power amplifier to give us the necessary power. For this part, we used the 2N3904 and 2N3906 NPN and PNP transistors because they were in our lab and convenient. To get a little more power out of this stage, yielding a better read range, you can use power MOSFETS.

The second stage in our reader circuit is the envelope detection and filtering stage. In order to retrieve data from the tags in our ID cards, it is necessary to separate out the actual modulation envelope from the carrier signal. We started with a simple RC low-pass filter with an RC time constant designed to filter out most of the 125-kHz signal with minima. We also employed a diode to half-wave rectify the signal to make things simpler down the line.

Photo 3 shows the stage’s output. As you can see, although there is definitely a visible ripple from the carrier signal, the entire waveform seems to oscillate along the envelope, which is exactly what we were aiming for.

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Photo 3—Check out the incoming signal once it passes through the half-wave rectifier and RC filter. There is clearly a 125-kHz ripple. The envelope is now the defining part of the signal.

Next, the signal is processed through a cascade of active filters. The aim of these filters is to both completely remove the carrier frequency, as well as give the modulating frequencies adequate gain to saturate the op-amps powering the filters, thereby creating a square wave that can be interpreted as a digital signal. The microID reference circuit provided the design for these. It uses cascading twin-t band-pass filters in order to provide gain to the modulating frequencies relative to all other frequencies. After this, we put the signal through an active low-pass Butterworth filter to give even more gain to frequencies within the original passband and quash all high frequencies, including the carrier signal. The Bode plot in Figure 3 illustrates the effects of the cascade.

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Figure 3—This is a Bode plot of each stage of the cascaded filters. The output of the first Twin-T filter is in blue, the second is in red, and the output of the Butterworth filter is in green. Notice the 1-dB point at roughly 30 kHz. This stage’s output should be a square wave at this frequency (idle frequency) when no card is present.

Now we have a square wave signal that oscillates at both of the modulating frequencies when an ID card is placed in the reader antenna’s proximity. Lastly, we put the signal through a comparator and voltage divider to generate a nice square wave at TTL levels so that it could be further processed and analyzed.

Technically, from the output of the comparator, we should have been able to read and interpret data from the card using a timer interrupt. We quickly realized, however, that by doing this we would cripple the system’s functionality. In order to accurately measure the frequency of the incoming datastream, we would realistically need to sample at 125 kHz, which meant that with a clock rate of 16 MHz, we would have 128 clock cycles to run the rest of our program before the next interrupt. That would have been extremely difficult to implement along with the rest of our system, especially because beyond just general code storing and checking, we planned to implement a communications protocol that could potentially block the interrupt. Additionally, in practice, we found this method for gathering data somewhat unreliable. Looking for an alternative method to obtain data, we found yet another brilliant design in the Microchip reference guide that made use of flip-flops and a decade (Johnson) counter.

The rationale behind this “data formatting” stage was simple: we needed to slow down the incoming signal so the ATmega32 could analyze it without limiting the functionality of our security program. It also has the added benefit of creating a signal that is only high when a 12.5-kHz pulse is received and is zero otherwise (as opposed to switching between logic 1 and logic 0 at different frequencies).

Implementing this stage was slightly complicated, but it didn’t require too many extra components. The purpose of the first flip-flop is to generate extremely short pulses at its clock frequency, which we made the TTL output from the comparator. The length of these pulses are directly determined by the size of the resistor used to bridge ~Q and ~CLR, and these are used to reset the decade counter and clock the second flip-flop. Photo 4 illustrates this circuitry a little more clearly.

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Photo 4—Channel 1 is the TTL-level output of the comparator after the filter stage. The short pulses in Channel 2 are created from the first flip-flop. The pulse widths after the flip-flop are roughly 350 ns.

The decade counter is a 1-hot counter that shifts the ACTIVE pin with each clock cycle. Because our two modulating frequencies are integer divisors of our carrier frequency (12.5 = 125/10 and 15.625 = 125/8), it was convenient to use the 125-kHz signal output from the microcontroller for the carrier signal as this clock cycle. The slower frequency counts as logical 1 and the counter is reset at the modulating frequency, so all we had to do was take the pin corresponding to 10 clock cycles in order to determine if we were dealing with a one or zero. The purpose of the second flip-flop is to lengthen the duration of that one or zero and give us a constant datastream to be ported to the ATmega32 (see Photo 5).

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Photo 5—Channel 1 is the TTL-level output of the comparator after the filter stage. Channel 2 is the datastream from the Data Retrieval stage. Notice how Channel 2 is high only after a 12.5-kHz pulse is observed. Both of the signals are used by the ATmega32 to determine the tag data.