February
2005, Issue 175
A
Look at the M16C Lineup
M16C
CORE
The
M16C core uses two identical register banks along with
six other system registers (see Figure 2). Each register
bank has two 16-bit registers (R0 and R1) that also
can be used as 8-bit registers (R0H/L and R1H/L). Two
additional 16-bit registers (R2 and R3) can be used
along with R0 and R1 as 32-bit registers (R2R0 and R3R1).
In a similar manner, 16-bit address registers (A0 and
A1) can be combined as a 32-bit address register (A1A0).
The 16-bit frame base register is used for signed relative
addressing. The B flag in the FLG register selects the
register bank.
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(Click
here to enlarge)
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Figure
2—This chart shows the registers that comprise the
M16C core CPU and addressing space that contains
RAM (SFR and data) and flash memory (data, code,
and interrupt) spaces. |
The
additional registers include a 20-bit program counter
and two 16-bit stack pointers: the internal stack pointer
(ISP) and the user stack pointer (USP). A stack pointer
is selected by the U flag in the flag register (FLG).
The 20-bit INTH/L (variable vector table base pointer)
is used as the base address for variable interrupts
18 through 255. The 16-bit static base register (SB)
is used for unsigned relative addressing. The 16-bit
FLG contains the system flag bits.
The
address space covers 1 MB. It is divided into areas
for the FSR (control registers for all internal peripherals),
RAM (variable scratch space including the stacks), internal
flash memory (data), external memory space, and internal
flash memory (code and interrupt vectors). The actual
flash memory and RAM space are determined by the size
of the memory in any particular device, with the flash
memory space decreasing and the RAM space expanding
upward.
Protection
features include main clock stop detection, a watchdog
timer, a protect register, and special instructions.
The protection register prevents the CPU from changing
a register’s value if the program goes off into the
boonies. In addition, if the CPU comes upon an undefined
instruction (e.g., an unprogrammed area of memory),
it will branch to an undefined instruction interrupt
vector where you can take charge and get things back
on track.
On-chip
flash memory offers single-voltage programming via a
serial ISP with automatic data rate detection. You can
rewrite internal flash memory under program control
as well. However, there are features to prevent accidental
erasure. You also can prevent external access to the
flash memory by using a security ID code without ID
and access.
