Issue 163 February 2004
The Growth of the Atmel AVR Family

---

---

Start • Instruction Set • Security for Smartcards • Thermistor • Talk and Listen to XPORT • Plug It In • Sources and PDF

Each time I look at my lawn (I use the word “lawn” loosely), I can’t help but think that if I would treat it to a bit of weed killer, I would have a nicer-looking yard. I don’t do this for a number of reasons. First, I like the look of green, as opposed to brown dying weeds. Second, I’d have to mow it on a weekly basis rather than a monthly basis. My lush green weeds seem to grow at a much slower rate than my neighbor’s patchy tufts of green grass. On the sunny side of the yard, I have a crop of nice green vegetation (albeit not grass). On the shady side, I have a nice carpet of cushy green moss—and moss doesn’t need trimming at all! I feel sorry for the lawn-care folks who constantly call and want to help me rid the area of weeds. They just don’t get it.

I used to play golf. Yes, manicured courses look great. But it just isn’t high on my list of priorities to sink a lot of money into my lawn to bring it up to perfection. I know someone who hates grass enough to drop mulch all over it. Now, he doesn’t even need a lawn mower! Although I haven’t gone to that extreme, I’ll choose the hammock over the mower and live amongst my green weeds.

I keep with the ideas that seem to work for me. As you know, I’ve always been a big fan of flash memory-based microcontrollers. Atmel began its AVR line of in-circuit programmable, flash memory-based processors in 1997. What were only four products just a few years ago have blossomed into a dozen or so today. You don’t get this kind of growth in a product line unless the first seeds have produced a bountiful harvest. Atmel credits this to a soaring price performance level.

WHAT IS AVR?

The CPU—which was developed by a pair of researchers in Trondheim, Norway prior to 1995—resembles most RISC processors, although it has smaller registers with most of the instructions running in a single cycle. A well-defined I/O structure with an internal oscillator, timers, UART, SPI, pull-up resistors, pulse width modulation, ADC, analog comparator, and a watchdog timer limit the need for external components. AVR instructions minimize the size of your program whether you write in C or assembly. The AVR will optimize costs and get your product to market quickly by way of on-chip/in-system programmable flash memory and EEPROM.

There are actually three separate spaces mapped into an AVR microcontroller. The address space is a linear 64 KB in a 16-bit word format (16-bit instructions). The program counter covers the complete flash memory (word) range of each part. There are two data spaces, one for EEPROM (when available) and the other for SRAM. As you can see in Figure 1, 32 general-purpose registers (0x00–0x1F) combine with the ALU to make up the central core. The AVR uses Harvard architecture (separate memories and buses for program and data). Almost half of the instructions are executed in one clock cycle with the CALL and RET instructions requiring up to five cycles. (They must adjust the stack.)

(Click here to enlarge)

Figure 1—The AVR CPU core uses 32 general-purpose registers having direct access to the ALU. A generous portion of peripherals is interfaced through the system address and data bus. Total ISP gives access to both flash memory and optional EEPROM memories.

In a typical ALU operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file in one clock cycle. Six of the 32 registers (0x1A–0x1F) can be used as three 16-bit indirect address register pointers (X, Y, and Z) for data space addressing (enabling efficient address calculations). Address pointer register Z (0x1E–0x1F) also can be used as an address pointer for look-up tables in flash program memory.

The I/O memory space contains 64 addresses for CPU peripheral functions as control registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the data space locations following those of the register file (0x20–0x5F). Larger devices have extended I/O addresses (0x60–0xFF) in data space.

Figure 2 shows the linear make up of the data space including the register file, I/O registers, extended I/O registers, and the internal data SRAM. On the ATmega169, there are 1024 bytes of available RAM beginning at address 0x100.

Figure 2—The data space consists of general-purpose registers and I/O registers. Devices stuffed with peripherals use an extended I/O register space. Note that 1 KB of internal SRAM begins at address 0x100 for the ATmega169.