Circuit Cellar Issue 151 Jeff Table 1






Table 1—In the lower part of the MC68HC908Qxx address space, there are 128 bytes of RAM between $0080                              and $00FF. As you now know, the majority of the 
 status, control, and data registers are between $0000 and $003F.

Address space	Registers
$0000	Port A data register (PTA)
$0001	Port B data register (PTB)
$0002-$0003	Unimplemented (two bytes)
$0004	Data Direction register A (DDRA)
$0005	Data Direction register B (DDRB)
$0006-$000A	Unimplemented (5 bytes)
$000B	Port A Pull-up Enable register (PTAPUE)
$000C	Port B Pull-up Enable register (PTBPUE)
$000D-$0019	Unimplemented (13 bytes)
$001A	Keyboard Status and Control register (KBSCR)
$001B	Keyboard Interrupt Enable register (KBIER)
$001C	Unimplemented
$001D	INT Status and Control register (INTSCR)
$001E	Configuration register 2 (CONFIG2)
$001F	Configuration register 1 (CONFIG1)
$0020	TIM Status and Control register (TSC)
$0021	TIM Counter register high (TCNTH)
$0022	TIM Counter register low (TCNTL)
$0023	TIM Counter modulo register high (TMODH)
$0024	TIM Counter modulo register low (TMODL)
$0025	TIM Status and Control register channel 0 (TSC0)
$0026	TIM Channel 0 register high (TCH0H)
$0027	TIM Channel 0 register low (TCH0L)
$0028	TIM Status and Control register channel 1 (TSC1)
$0029	TIM Channel 1 register high (TCH1H)
$002A	TIM Channel 1 register low (TCH1L)
$002B-$0035	Unimplemented (11 bytes)
$0036	Oscillator Status register (OSCSTAT)
$0037	Unimplemented
$0038	Oscillator Trim register (OSCTRIM)
$0039-$003B	Unimplemented (3 bytes)
$003C	Adc Status and Control register (ADSCR)
$003D	Unimplemented
$003E	Adc Data register (ADR)
$003F	Adc Input Clock register (ADICLK)
$0040-$007F	Reserved (64 bytes)
$0080-$00FF	RAM (128 bytes)
$0100-$27FF	Unimplemented (9984 bytes)
$2800-$2DFF	Auxiliary ROM (1536 bytes)
$2E00-$EDFF	Unimplemented (49,152 bytes)