Issue
151 February 2003
Newcomer
Nitron
Motorola's
Leading 8/16-Pin MCUs
MON
Pin
function is of the utmost importance, especially
on devices with low pin counts. Adding a monitor
function to a micro usually means dedicating I/O
to that function. The ’908Q device checks the I/O
state during reset release and uses I/O PTA0 as
a half-duplex serial communications channel for
user access to the preprogrammed monitor program.
When
the device is empty (i.e., erased), Monitor mode
is entered using an internal or external oscillator
without special voltages. After it’s programmed,
Monitor mode is forced only via an external oscillator
and a high voltage on the IRQ input (VCC + 2.5 up
to VCC + 4).
Serial
communication is 9600 bps using an 8N1 format with
the internal oscillator (or 9.83 MHz with the external
oscillator). Six commands are available via the
monitor ROM: READ memory, WRITE memory, IREAD indexed
read, IWRITE indexed write, READSP read stack pointer,
and RUN execute user program.
Each
byte received from the host is echoed back for error
checking. Table 3 lists the command
opcode and operands. A security feature prevents the
unauthorized reading of flash memory if the first 6
bytes after reset don’t match the bytes programmed in
the $FFF6-to-$FFFD addresses (i.e., interrupt vectors).
The host sends a break (10 zero bits) if a match is
attained. A security failure will allow monitor commands,
including the execution of a mass erase function. Thus,
you can recover control of the device without revealing
the programmed code.
I/O
Devices
with low pin counts require a port pin to function
in multiple modes in order to achieve the highest
level of versatility. Port pins are configured as
digital input or output (with the exception of PTA2,
which is only input) through the data direction
register (DDRx).
Any
input bit can have an internal pull-up that’s enabled
via the Port X pull-up enable register (PTxPUE).
All of Port A’s inputs can be used as an external
interrupt through the keyboard interrupt module
(KIM). These are configured for edge or level detect
via the MODEK bit in the keyboard status and control
register (KBSCR).
The
KEYF bit indicates input detection and allows you
to poll for this action. The IMASKK bit enables/disables
the external interrupts. The port bits are read
from or written to using the PTx (data register).
Bit 6 of PTA has a special function, the AWUL bit
can enable/disable an automatic wake-up from Stop
mode in the KIM.
ADC
The
ADC uses linear successive approximation to convert
an analog input into an 8-bit digital representation
in 16 ADC clock cycles. Analog input is routed to
the ADC from one of four bits via a multiplexer.
The maximum ADC frequency is 1 MHz. When the system
execution cycle is faster than 1 MHz, an ADC prescaler
(divide by 1/2/4/8/16) is used to reduce the ADC
clock. This ADC supports both single and continuous
conversion with a conversion-complete flag and interrupt
available. As a rule of thumb, wait one conversion
time between channel changes and enabling the ADC.
