Issue
151 February 2003
Newcomer
Nitron
Motorola's
Leading 8/16-Pin MCUs
OSC
All
of the standard oscillator configurations are available
on the ’908Q. Take note of the external RC, crystal
(or oscillator), and an internally generated fixed
clock frequency (12.8 MHz).
Two
internal clocks are derived from the oscillator.
One is a divide-by-2 that’s used by the system integration
module (SIM) and COP. The other is a divide-by-4
that’s used by the CPU as an instruction cycle clock
(bus clock).
The
internal oscillator is adjustable ±25% to within
less than 5% by setting a trimming register with
a value other than the default value of $80. (Note
that values less than $80 slow down the oscillator,
and values greater than $80 speed it up.)
An
oscillator divide by 4 (bus clock) is an option
available for calibration purposes on pin OSC2.
The maximum external frequency is 8 MHz for 5-V
operation and 4 MHz for 3-V operation.
COP
The
free-running COP counter will interrupt the device
if it overflows. This is an attempt to recover from
runaway code. In order to prevent the COP from interrupting
during the normal execution of code, your code must
clear the COP counter at regular intervals.
The
COP counter is a 6-bit counter clocked by the divide-by-12
SIM counter (clocked from the oscillator). The overflow
can come from stage one or six of the COP counter
depending on the COP rate select (COPRS) bit in
the CONFIG1 register. That’s either a 1- or 32-ms
overflow at the maximum oscillator frequency (8
MHz). The COP is cleared by writing any value to
the $FFFF address.
LVD
The
’908Q has low-voltage detect (LVD) circuitry that’s
used to create a reset if VCC falls below a VTRIPF
voltage or doesn’t rise past a VTRIPR voltage. An
LVD output of logic 1 indicates an improper VCC;
it’s polled or used to reset the device.
Four
LVD configuration bits are located in the CONFIG1 register.
Because the ’908Q devices run on 3 or 5 V, a LVI5OR3
bit changes the VTRIP levels for the different VCC levels.
The LVIPWRD bit enables/disables the LVD function, the
LVITSTD bit enables/disables the device reset function,
and the LVISTOP bit enables/disables the LVD function
during Stop mode.
