Issue
151 February 2003
Newcomer
Nitron
Motorola's
Leading 8/16-Pin MCUs
VOLATILE
MEMORY
The
volatile memory consists of user RAM, reserved registers,
and I/O. As I mentioned in association with the SP,
there are 128 bytes of RAM between $0080 and $00FF (see
Table 1). Most of the control, status, and data registers
are within the $0000-to-$003F address space.
| Table
1—In the lower part of the MC68HC908Qxx address
space, there are 128 bytes of RAM between $0080
and $00FF. As you now know, the majority of the
status, control, and data registers are between
$0000 and $003F. |
Additional
RAM status and control registers are located in the
$FE00-to-$FE0C upper address space in addition to $FFBE,
$FFC0, and $FFFF (see Table 2). The $FFFF location performs
two functions. When this address is read, it contains
the LSB of the reset vector. On the other hand, when
this address is written to, it resets the computer operation
properly (COP) watchdog counter.
| Table
2—Additional RAM status and control registers
are located in the upper part of the MC68HC908Qxx
address space. Take a look at $FE00 through $FE0C
in addition to $FFBE, $FFC0, and $FFFF. |
TIM
The
timer interface module (TIM) is a two-channel timer
that provides timing reference, input capture, output
compare, and PWM functions. Figure 3 illustrates the
TIM. The prescaler has seven prescaler select bits for
a divide by 1/2/4/8/16/32/64 from the internal bus clock.
The 16-bit counter (TCNTH:TCNTL) can be configured to
count up until matching the TMODH:TMODL registers and
then reset to zero or free run. TCNTH:TCNTL can be read
at any time without disturbing the count. The timer
overflow can cause an interrupt.
|
(Click
here to enlarge)
|
Figure
3—The timer interface module (TIM) has three main
parts: a prescaler, 16-bit counter, and capture/compare
unit. Two independent channels use an I/O either
as input for counting or output for signal generation.
|
Two
pins, TCH0 and TCH1, can serve as inputs to capture
separate events. On input, the 16-bit counter value
is latched into separate capture/compare registers
(i.e., TCH0H:TCH0L and TCH1H:TCH1L). The input capture
edge polarity can be rising, falling, or both. In
addition, the capture can cause an interrupt.
It’s
possible to use the same pins as outputs controlled
by the capture/ compare registers. In this mode
the output pin can be set, cleared, or toggled on
a match.
When
used in conjunction with the 16-bit timer overflow,
PWM outputs can be created. If the capture/compare
register values are changed asynchronously, transition
glitches can occur in the counts. This isn’t a problem
in most applications. Linking the two channels together
makes synchronous changes. In this case only one
output is available as the channels are used in
an alternating fashion.
