Issue
151 February 2003
Newcomer
Nitron
Motorola's
Leading 8/16-Pin MCUs
THE
CORE
As
you can see in Figure 2, the CPU consists of a control
unit and execution unit. The former is a finite state
machine that’s responsible for generating all of the
execution unit’s control signals; it uses four clock
cycles to prepare the needed output (one execution cycle).
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(Click here to enlarge)
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Figure
2—The HC08 CPU is based on a control and execution
units. The CPU uses five registers. The 16-bit program
counter can reach the total address space. |
The
execution unit contains five registers: an accumulator
(A), control code register (CCR), stack pointer
(SP), program counter (PC), and index register (H:X).
In addition, it includes the arithmetic logic unit
(ALU) and special-function logic for the DAA, MUL,
and DIV instructions.
The
8-bit A register holds operands and the results
of arithmetic/logic operations. The 8-bit CCR register
contains six flags: overflow, half-carry, interrupt,
negative, zero, and carry/borrow. Although the 16-bit
SP register can reach the full address space, make
sure it remains in the RAM space located between
the $0080 and $00FF addresses on these devices.
The
SP is initialized to the end of RAM and works downward.
In addition, the 16-bit PC register can also reach
the full address space. At reset, the program counter
is loaded with the address in the reset vector at
the $FFFE:$FFFF addresses. The 16-bit H:X register
is used to index or point to a memory location.
FLASH
MEMORY
The
on-board flash memory is in-circuit reprogrammable
thanks to an internal charge pump. The linear memory
array (1.5 or 4 KB) is located at the top of the
16-bit memory space and extends downward from $FDFF.
There is an additional 48 bytes ($FFD0 to $FFFF)
for interrupt vectors.
One
block of 64 bytes is the minimum number of bytes
that can be erased at one time (i.e., beginning
at any address $xx00, $xx40, $xx80, or $xxC0). The
maximum number of bytes that can be programmed at
one time is one row of 32 bytes (i.e., beginning
at any address $xx00, $xx20, $xx40, $xx60, $xx80,
$xxA0, $xxC0, or $xxE0).
The
flash memory control register (FLCR) controls the
erase and program operations. Four bits are responsible
for all of the operations: high-voltage enable (HVEN)
enables the internal charge pump; the mass erase
control bit facilitates total erasure; the erase
control bit permits block erasure; and the program
control bit (PGM) enables row programming.
Protection
against the unintentional erasure or programming
of the flash memory is carried in the flash block
protect register (FLBPR). This register indicates
the starting block to be protected up to the end
of memory $FFFF. The FLBPR prevents the HVEN bit
from being set when attempting to erase or program
a protected block, including the block containing
the FLBPR.
So,
after it’s programmed, you cannot change FLBPR without
applying a high voltage to the IRQ pin forcing the micro
into Monitor mode after a reset. Then, you can perform
a mass erase via the monitor.
