Issue 127, February 2001
Working with AVR Microcontrollers

The Software

AVR processors execute an instruction set that consists of 118 basic instructions. The larger ATmega parts have additional instructions to support their extended memory addressing range. Smaller devices with no internal SRAM (other than the 32 registers) do not support instructions that involve accessing the additional memory.

AVR processors include special function registers that control various things such as the direction of the I/O pins (input or output) and timers’ mode of operation. The AVR instruction set permits you to set and clear individual bits in the I/O ports and in the special function registers.

As mentioned earlier, six of the 32 registers can be paired as pointer registers for accessing either SRAM (in processors that have SRAM) or program memory. There are specific instructions that access memory using these register pairs and specific instructions that permit simple 16-bit math for manipulating each pair as a single entity.

Several instructions are dedicated to moving data using the pointers. These permit the pointer register pair to be pre- or post-decremented (or incremented) when a move is performed. These special instructions simplify the software and prevent potential race conditions that could be caused by an interrupt occurring between a move and increment/decrement instruction pair.

AVR processors support several interrupts. Which interrupts, of course, depend on which peripherals are included in your chip. Interrupt vectors are located in the flash memory starting at location 0000. The first vector is the reset vector and the interrupt table grows upward from there. Each vector location is one-word wide, so the table consists of a string of jumps to the various interrupt service routines.

The AVR processors include a stack to save return address for calls and interrupt servicing. On smaller devices without SRAM (such as the ’1200) the stack is implemented in the hardware and is of limited size. On devices with internal SRAM, the stack is located in SRAM and accessed via a stack pointer register. On devices with less than 256 bytes of RAM, the stack pointer register, SPL, is 8 bits. On devices with more than 256 bytes of SRAM, the stack pointer is a register pair (SPH and SPL) to access the additional space. The software must initialize SPH and SPL (typically to the top of SRAM) before enabling interrupts or executing any subroutine calls.

On AVR devices that do not contain internal SRAM, the stack is only three levels deep and there is no stack pointer to initialize. If you use nested interrupts (an interrupt service routine can be interrupted), be careful not to overflow the stack. Also, the stack can be used only to store return addresses; the PUSH and POP instructions are not operational on these parts.