January 2006, Issue 186

Third-Generation Rabbit
A Look at the Rabbit 4000

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NEW PERIPHERALS

In addition to the changes to existing peripherals, we’ve added four new ones. Two of them are pretty simple, but the last two actually rival the CPU in complexity.

Calling the first new peripheral a peripheral is a little misleading because it’s really just a small piece of RAM. Besides being located in the internal I/O space, this 32-byte RAM has two other unique features. First, this memory is powered from the same power plane as the real-time clock and is normally supplied by a battery. This memory is useful for holding data that isn’t appropriate to write to flash memory, such as an encryption key. Second, because the data in this memory may be sensitive, whenever any attempt is made to enter Program or Debug mode, the memory is automatically cleared. Connecting one of the programming pins to a tamper-detect mechanism on an enclosure will provide security for any data held in this RAM.

The second new peripheral is timer C, which provides functionality that was not available in the existing timer resources. Although timer A provides a number of 8-bit timers and timer B is 10 bits, timer C is up to 16 bits with a programmable count limit.

Along with the programmable count limit are four match registers, two each to set and reset a status bit or generate an interrupt. These features enable variable frequency pulse-width or pulse-position modulation signals to be easily generated for use with things like servos.

More and more embedded systems require network connectivity, so the Rabbit 4000 includes a full-featured 10BaseT controller. This network port provides all of the features necessary to communicate efficiently over a network.

The network port, which operates either half-duplex or full-duplex, contains a complete auto-negotiation function to automatically select between these two modes. Of course, this auto-negotiation can be disabled to force a particular mode.

The network port doesn’t require an external physical interface (PHY), but instead needs only a few inexpensive external components to connect to the cable. This was one of the primary design goals for the device.

In addition to the usual error counters, network timers, and so on, we included some hardware to make handling the higher-level protocols easier. For example, TCP/IP makes use of a checksum covering the entire message. The network port automatically calculates this checksum to reduce software overhead.

There are several reasons why we went with just a 10-Mbps network port rather than a 10/100 port. Besides several implementation issues, which include requiring an external PHY and on-chip buffers, Rabbit’s experience in providing network-enabled controllers indicated that 10BaseT was sufficient for this generation.

The bus bandwidth required for 10 Mbps is low enough that the design doesn’t need on-chip buffers. Instead, there is a 16-byte FIFO in the transmitter and a 32-byte FIFO in the receiver. Coupled with the powerful new DMA controller, the network port only needs one interrupt per received or transmitted frame.

The new DMA controller contains eight independent channels for efficiently moving data between any combination of memory, internal I/O, or external I/O. Rather than requiring programming by the CPU, these DMA channels use buffer descriptors in memory to control DMA operation.

Figure 2 (p. 40) shows the structure of a buffer descriptor. Each descriptor is either 12 or 16 bytes in length. All DMA addresses are physical addresses. Four byes are reserved for the source address and destination address, even though only 3 bytes are used. This makes it easier for the CPU to build the descriptor using 32-bit operations.

(Click here to enlarge)

Figure 2—The DMA uses buffer descriptors in memory to control its operation. One command from the CPU tells the DMA to begin operation.

Two bits in the control byte identify the source address as an incrementing memory address, a decrementing memory address, a fixed external I/O address, or a fixed internal I/O address. Another 2 bits perform the same function for the destination address.

To increase performance, the DMA doesn’t fetch the unused bytes in the descriptor. If either address is tagged as I/O only, the 2 least-significant bytes are fetched. This is because I/O addresses are always 16 bits in the Rabbit 4000.

The Link Address field is optional and enabled by a bit in the control byte. If no link address is present, the next descriptor is contiguous with this one. If the link address is present, it points to the starting address of the next descriptor. This creates a linked list of buffer descriptors.

The Buffer Length field is self-explanatory. It allows for buffers of up to 64 KB in length.

One of the remaining bits in the control byte tags the descriptor as the final descriptor. The DMA stops after this buffer is complete and must be restarted by CPU command.

Another bit enables an interrupt at the completion of this buffer. In most cases, the operation of the DMA is so automatic that an interrupt on buffer completion isn’t necessary.

Any internal peripheral can be used with the DMA, and the DMA recognizes certain internal I/O addresses and automatically connects to the relevant request signals so that the peripheral can control the data transfers. This works well with those peripherals that have a fixed address for data (e.g., the serial or network ports), but would be a problem with the PWM channels or timer C because of the multiple I/O addresses required to program them.

To address this issue, both of these peripherals have a new block transfer address. Writing repeatedly to this address automatically steps through all of the necessary PWM or Timer C control registers to allow for DMA control of these peripherals.

Receive messages from either the serial port or network port are unlikely to finish on a buffer boundary, so the DMA automatically closes a buffer after transferring the last byte of a message. The DMA also automatically writes a status byte that’s read from the serial or network port that contains the frame status.

This status byte is written to the status byte in the first buffer descriptor. At the same time, the DMA stores the number of completed buffers, plus the byte count of the current buffer, in internal registers. All of this information enables the CPU to quickly determine the status and length of a received message.

Transmit messages to either the serial or network port also require some special handling. This is because the last byte of a message must be identified so that CRC can be appended.

The last bit in the control byte of the buffer descriptor tags this descriptor as the last one for the current message. The DMA then writes the last byte of this buffer to a special serial or network port address. This is what tags the byte as the last byte in a transmit message.

One DMA feature that isn’t controlled through the buffer descriptors is the pattern match capability. This feature enables the DMA to terminate a buffer after the transfer of a particular byte value. This byte value is programmable and can also have any number of bits masked off from the comparison.

This feature is particularly useful with point-to-point protocol (PPP) links. PPP operates over ordinary serial links and uses a special byte as a message delimiter. Placing messages in separate buffers greatly simplifies the software necessary to handle this protocol.

The final DMA feature that I’ll mention is the timed transfer option. The DMA contains an internal timer that generates a periodic transfer request. This request can be used to write to a parallel port to generate periodic signals without any CPU overhead. It can also be used to repetitively read or write an external ADC or DAC.