The AVR-based FPSLIC II is the industry’s first family of dynamically reconfigurable System-on-a-Chips (SoCs) that enables multiple interfaces, peripherals, and operators to share the same silicon at different times. Silicon sharing is important in power- and space-constrained systems. These devices must perform multiple functions (e.g., camera, MP3 player, and phone) without sacrificing battery life, product size, and affordability.

Back-end reconfiguration EDA tools enhance the FPSLIC II’s silicon-sharing capability. The tools are the first to automate the implementation, timing, and control of the silicon-sharing process.

The SoC integrates a 25-MIPS, 8-bit AVR processor with 36-KB program/data SRAM, a hardware multiplier, peripherals, and a dynamically reconfigurable FPGA with 256 to 2,300 core cells. A single piece of silicon can implement multiple interchangeable peripherals, computational operators, and bus interfaces, including UART, SDIO, PCI, PCMCIA, HDLC, and Ethernet.

A library of reference designs for interfaces, peripherals, and hardware accelerators is available. It includes Ethernet, memory, an SPI, SDIO, a multimedia card, DMA, speech synthesis, ADPCM, audio codec interfaces, and DES/triple DES encryption algorithms. A library of pre-routed drag-and-drop coprocessors and interfaces will be introduced later this year.

The FPSLIC II family of devices is available in lead-free, 144-pin TQFP and 208PQFP packages. Prices start at $4.50 in quantities of 100,000 units for the AT94K05AL-25BQU 256 core cell device.

Atmel Corp.
www.atmel.com