Answer 1—The 74LS161A is a 4-bit binary counter that’s wired to count repeatedly from three to 15 and start over again, giving a total of 13 states. The QB output pulses three times during this 13-state sequence, so the circuit overall is multiplying the input clock by a factor of 3/13.

The interesting thing about this particular ratio is that, given the input clock of 16 MHz, the output has a frequency of 3.6923 MHz, which is just 0.16% high relative to a standard data rate generator crystal frequency of 3.6864 MHz. Therefore, this circuit can be used in lieu of a separate crystal for generating the 16× clock required for standard serial I/O port data rates up to 230.4 kbps.

Contributor: David Tweed