Answer 2—A quad two-input multiplexer (a single TTL chip) on the high-order bits of the SRAM address bus can be used to map the 12 bits of address required for row-column addressing (5 bits for row, 7 bits for column) down to the 11 bits of a linearly addressed 2-KB memory, as shown below. 

 The first 64 bytes of each line map into contiguous groups of 64 bytes starting at the beginning of memory. This occupies the first three-quarters of the SRAM. The last quarter of the SRAM is used to hold the last 16 bytes in each line. The multiplexer is controlled by the high-order column address bit (A6) to rearrange how the high-order row and column address bits are connected to the SRAM.

As long as the processor writing to the display RAM and the hardware reading it out to refresh the CRT are using the same mapping, the actual location used within the RAM chip for any particular character doesn’t really matter.

Contributor: David Tweed