Answer 5—First of all, it’s clear that if the FIFO is inserted into a point in the path where the data is in serial form, it only needs to be 1 bit wide. The important question is how deep must it be?

One of the key requirements is that the FIFO must not create any more “bit slips” (dropped or repeated bits) than absolutely necessary. A dropped bit occurs when the FIFO overflows, as a result of the input bit rate being temporarily higher than the output bit rate for too long. A repeated bit occurs when the FIFO underflows because the input data rate is too low. It is important that the FIFO not create bit slips at any other time while it is operating in the permissible region between underflow and overflow.

Furthermore, whenever a bit slip must occur, it would make sense to do the slip in such a way that the next slip is postponed as long as possible. This can be accomplished, for example, by reinitializing the FIFO to its half-full state whenever a slip occurs, giving the maximum room for jitter/wander in either direction.

In order to meet the requirements outlined previously, a FIFO must contain at least two storage elements (flip-flops). But such a FIFO would be extremely prone to bit slips whenever the input and output clocks are closely aligned. However, a FIFO with one additional bit of depth would always be able to tolerate one whole bit time of clock drift in either direction immediately following any bit slip. Therefore, three bits of depth is the minimum that is worth implementing. Such a FIFO can be implemented in an FPGA using seven to nine flip-flops and a handful of additional gates.

Contributor: David Tweed