Answer 5—An SDRAM chip uses a delay-locked loop (DLL) to internally compensate for the delays associated with its pin input and output buffers. A typical DLL has a lock range of about 2:1, which directly determines the range of clock frequencies that the chip can work with.

The DLL allows the chip to create an internal clock that is offset from the input clock in such a way that the output pins (primarily the data bus and data strobes) appear to have zero clock-to-out delays. The delays of the chip’s input and output buffers are hidden, simplifying the design of the SDRAM controller logic.

Contributor: David Tweed