April
2004, Issue 165
Test Your EQ:
Each
month, Test Your EQ presents some basic engineering
problems for you to test your Engineering Quotient.
What's your EQ?
|
Problem
1—What
are the correct units for bulk resistivity?
Answer
Problem
2—What are the correct units for resistivity
in materials constructed as thin sheets?
Answer
Problem 3—The figure shows one way of generating
a gated clock signal. What’s wrong with this approach?
How can this be fixed?
Answer
Problem
4—The following circuit is a glitch filter for
a clock signal.
The MAJ3 gate is a special primitive available in some
FPGA families. Its output is the same as the majority
of its inputs; in other words, if any two inputs are high,
the output is high. How exactly does it work, and what
would be the effect of inverting the output of the delay
line?
Answer
Problem
5—Most FPGA technologies are designed so that
the minimum clock-to-output delay of a flip-flop will
meet the input hold time of a second flip-flop that is
clocked by the same clock signal. However, when building
long shift registers, it is often necessary to create
multiple clock signals with buffers in order to meet fanout
limitations. Keeping in mind that buffer delays vary with
process, temperature, and loading, comment on the following
three buffering schemes.
Scheme
1:
Scheme
2:
Scheme
3:
Answer
Problem
6—What is a PIN diode, and what are some of its
common uses?
Answer
Problem
7—Let’s assume you have an ideal voltage source
of 1 V, an ideal current source of 1 A, and an ideal diode.
How would you connect these items together to produce
a 1-A current source that has a voltage limit of 1 V and
a 1-V voltage source that has a current limit of 1 A?
