Answer 5—Scheme 1 is commonly seen, but it’s probably the worst choice of the three. The delay of the buffer driving CLKB directly reduces the hold time margin going into the fifth flip-flop, probably violating the specification. This is exacerbated by the fact that signal D4 is lightly loaded, so the clock-to-output delay of the fourth flip-flop will be close to its minimum value.

Scheme 2 provides the highest operating speed because CLKA and CLKB will be nominally aligned. However, care must be taken so that the two buffers are physically close to each other to minimize differences in their characteristics over process and temperature variations. Also, they should have identical fanout and similar output network lengths to the fourth and fifth flip-flops.

Scheme 3 is the safest configuration for low- and medium-speed applications. Here, the upper buffer’s delay helps increase the hold time of signal D4 going into the fifth flip-flop.

A general rule of thumb for low- and medium-speed circuitry is that data and clocks should generally “flow” in opposite directions through major blocks of logic, wherever possible. However, beware of data signals that feed back to earlier stages of logic.

Contributor: David Tweed