Answer 4—The MAJ3 gate with its feedback connection becomes a kind of R-S flip-flop. If the input and the delayed input are both in the same state, then the output is forced to that state and any change on only one of the inputs will not affect the output. If a glitch whose duration is less than the delay appears at the input (and then at the delayed input), the output will be clean. If the input makes a longer-duration change to the opposite state, the output will follow after the delay has expired, and any messiness in the transition will be masked. The timing diagram below shows these features.

Inverting the output of the delay line, as shown below, has some interesting consequences.

Assume that the input and the output are already low and that the output of the inverter is high. Now any rising edge on the input will cause the output to immediately go high and stay there for the duration of the delay, regardless of any additional input transitions. After the delay has expired, the inverter’s output goes low, in effect “arming” the circuit for the next high-to-low transition. The net effect is to give you leading-edge switching in exchange for giving up isolated-glitch immunity, as shown below.

This shows an isolated input glitch getting stretched out to 20 ns; but, in reality, an input glitch might not make it cleanly through the delay line and inverter. In this case, the output will simply remain in the wrong state until the next real input transition.

Contributor: David Tweed