Answer 3—The circuit is almost guaranteed to produce glitches, especially if the gate’s propagation delay (A) is slightly less than the clock-to-output delay of the flip-flop (B), as shown in the following timing diagram. For simplicity, assume equal t_PLH and t_PHL throughout.

Note how the first rising edge of the clock is delayed through both the flip-flop and the gate, shortening the output pulse width (X) relative to that of the input (W). Also, the second rising edge of the clock forces the output high before the falling edge of the flip-flop can cut it off, creating a glitch that may or may not activate the subsequent logic.

It is better to arrange the logic so that both edges of the output pulse are controlled by the clock edges, effectively hiding the propagation delay of the flip-flop. One way to accomplish this is shown here:

As the timing diagram below shows, now the output pulse width is the same as the input pulse width, and the glitch is gone. The active (rising) edge of the output pulse is now one clock period later than in the original design, but it should always be possible to rearrange state machines to accommodate this.

The best solution of all, of course, is to avoid gated clocks altogether and use flip-flops that have “enable” inputs instead. In FPGA design, making a design fully synchronous often allows special global clock networks to be used, bypassing the usual limitations on fanout, skew, and routability.

Contributor: David Tweed