Test Your EQ
— Issue #144
Each month, Test Your EQ presents
some basic engineering problems for you to test
your Engineering Quotient. What's your EQ?
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Problem 1—The
circuit shown below is an adjustable output voltage regulator.
Assume that the basic opamp is ideal. Find the regulated
output voltage Vo.
Answer
Problem 2—A
dynamic RAM cell which holds 5V has to be refreshed every
20 ms so that the stored voltage does not fall by more
than 0.5V. If the cell has a constant discharge current
of 0.1pA, what is the storage capacitance of the cell?
Answer
Problem 3—Show
that the basic resistor-transistor logic (RTL) gate shown
below is a NOR gate.
Answer
Problem 4—In
general, what is the order of gate complexity relative
to the number of inputs to be counted?
Answer
Problem 5—
A full adder is a circuit with three inputs and two outputs,
and the output is a 2-bit binary number that gives the
number of "ones" on the inputs. Can you come up with a
circuit using only full adders that can count the number
of ones on 15 inputs?
Answer
Problem 6—
Now suppose you want to know if there are more than N
ones on the inputs, where N is presented as a 4-bit binary
number. Can you add this functionality using just full
adders (with perhaps some inverters)?
Answer
Problem 7—For
the circuit shown below VCC = 15V, hFE(min) = 30 and ib
= 100ľA. Find the minimum value of RL that will ensure
saturationtion.
Answer
Problem 8—What
is "comfort noise"?
Answer
Published: July-2002
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