Differences Between the TPU, TPU2, and TPU3

Differences Between the TPU, TPU2, and TPU3

The time processor unit (TPU), as any successful design, evolves and has been enhanced over the years. There are currently three versions of the TPU—TPU, TPU2, and TPU3—currently available on many Motorola microcontrollers.

The TPU was originally designed for the 68332 and has since been included on several 68300 and 68HC16 devices. Although the TPU proved extremely popular, the TPU2 was designed to meet the market’s need for more program memory. The TPU3 was then derived to cope with the higher clock speeds required in the move to the PowerPC architecture. A summary of the hardware differences between the three TPU derivatives is shown in Table1.

	TPU	TPU2	TPU3
Memory map	2 KB	8 KB	8 KB
Internal memory	2 KB ROM	4 KB ROM	4 KB ROM
Emulation memory	2 KB SRAM	4 KB FLASH	6 KB SRAM
Parameter RAM	200 bytes	256 bytes	256 bytes
Input digital filter	4 clocks	2,4,8,16,32,64,128 or 256 clocks	2,4,8,16,32,64,128 or 256 clocks
T2CLK edge detect	Rising only	Rising, falling or both	Rising, falling or both
Soft reset	No	Yes	Yes
Hardware output disable	No	Yes	Yes
Minimum TCR1 resolution	4 clocks (160 ns @ 25 MHz)	2 clocks (80 ns @ 25 MHz)	2 clocks (50 ns @ 40 MHz)
TCR1 prescaler divider	4 or 32	2, 4 or 32	Even values from 2 to 64
TCR2 prescaler divider	1, 2, 4 or 8	1, 2, 4 or 8	1, 2, 4, 8 or 16

Table 1—Here's a look at the features of the three TPU options.

As shown in Table 1, the total accessible memory maps on the TPU, TPU2, and TPU3 are 2 KB, 8 KB, and 8 KB, respectively. The cost of moving to a larger memory map was the loss of the "no parameter preload" option. This was necessary as the entry addresses on the TPU2 and TPU3 required two extra bits. On the TPU2 and TPU3 a paged memory system is used with 2 KB of memory per page. The entry table can jump to a state within any of the 2-KB banks but, once a bank has been entered, it cannot jump to another bank. It is possible to have multiple entry tables allowing more than one set of TPU functions in ROM, RAM, or flash memory at once.

The parameter RAM on the TPU leaves the two most significant parameters on each channel, except channels 14 and 15, unimplemented. This saves space on the TPU but makes it difficult to write functions that use the parameters from more than one channel. This arrangement has been changed in the move to the TPU2 and TPU3 and extra parameters have been added to accommodate more complex functions.

Two new features on the TPU2 and TPU3 are the soft reset and output-disable features. The soft reset feature allows the TPU to be reset independently of the microcontroller and the output disable feature allows the high-speed turning off of outputs. When the output-disable feature is enabled, there is only one gate delay between the signal being asserted and all of the TPU outputs going tristate. This is extremely important for applications like motor control, where it is essential that outputs be disabled as soon as possible after an error occurs.

As well as hardware changes between the TPU derivatives, microcode changes have also been implemented. A summary of the changes to the microcode is shown in Table 2.

	TPU	TPU2	TPU3
Timebase Match mode	Greater than or equal	Greater than or equal and equal only	Greater than or equal and equal only
Flags per channel	2	3	3
Current pin state condition	No	Yes	Yes
Negate MRL/TDL in format 3.	No	Yes	Yes
Clear DIOB, P or parameter with RAM sub-instruction	No	Yes	Yes

Table 2—Diffrent features means that the microcode for each derivative will also be slightly diffrent.

All three TPU derivatives use a unique greater-than-or-equal-to comparator feature which allows the TPU to determine if a time is in the past or the future. This is an extremely important feature for real-time systems where signals must be generated as accurately as possible. When performing the greater-than-or-equal-to calculation, only 15 bits on each of the TPU’s two 16-bit timebases are available because one bit is needed for the greater-than comparison. As some users indicated the need for the full 16-bit timebase range, the TPU2 and TPU3 were developed with an alternative equal-only feature. This feature can be used where the full range is required but the greater-than comparison is not necessary.

There are four other microcode changes between the TPU, TPU2, and TPU3:

Flags per channel—when writing TPU microcode, software flags are useful because they are simple to set and test. As an enhancement to the TPU, a third software flag has been added to each channel on the TPU2 and TPU3.
Current pin state—in the TPU, when testing the state of a pin, the state is latched on entry. Microcode instructions are required to obtain the current state. On the TPU2 and TPU3, it is possible to directly test the latched and current pin states.
Negate MRL/TDL—two new instruction formats that have been added are "negate match recognition latch" (MRL) and "transition detect latch" (TDL). These instructions clear a latch set after the occurrence of an event.
RAM zero operation—on the TPU, the only way to clear a parameter location is to load zero into a register and subsequently store that register. With the RAM zero operation, it’s possible to clear a memory location using the RAM subinstruction. The RAM zero feature can also be used to clear the "P" and "DIOB" registers that are used to access parameter RAM.