Published August 2001

FINE TUNING AN EMBEDDED IDEA

Part 2: Ethernet-Equipped RabbitCore Modules
by Fred Eady

Start • The Networking Core • Code Names and Comedy • Where and Why • Completing Initialization • Down to Business • Now What? • Sources and PDF

WHERE AND WHY

Now that we know where things are going to happen and some of the reasons why, the next logical step in the RTL8019AS initialization process is to condition all of the Rabbit 2000 microprocessor lines that interface to the RTL8019AS. This will allow the RCM2100 microprocessor to gain control of the RTL8019AS internal register set and, thus, the RTL8019AS itself.

The very first #define in Listing 1 brings you to the code snippet in Listing 2 . Now refer to the RCM2100 schematic. Note that PE2 and PE6 drive the RTL8019AS IORB and IOWB I/O control lines, respectively. The 0x44 value that is inclusive ORed to the port E data direction register (PEDDR and PEDDRShadow) designates PE2 and PE6 as outputs. Writing 0x44 to the port E function register (PEFR) changes the pins’ function from ordinary I/O pins to external I/O control signals.

Refer back to Listing 1. PD_WR1 is set for 0xC000 and PD_RD1 is defined as 0x4000. Here’s the reason why. When the code set up PE2 to become an I/O control signal, it was assigned to external I/O bank IB2CR (I/O bank two control register). The I/O address of IB2CR is 010 with this 3-bit value representing bit positions A15, A14, and A13, respectively. The binary representation of the base address for IB2CR is 0100 0000 0000 0000, or 0x4000. PE6 in the same manner now belongs to IB6CR. The upper three address bits for IB6CR are 110, which equates to 1100 0000 0000 0000, or 0xC000 which is exactly what Listing 1 states for PD_WR1.

Writing 0x90 to IB2CR makes PE2 an active ‘low I/O read strobe with three waits. The 0xA8 applied to the IB6CR results in converting PE6 to an active-low I/O write strobe with three waits. Address lines A0–A4 make up the five least significant bits. Using the IBXCR lines in conjunction with the A0–A4 bits allows read and write access to the RTL8019AS’s internal register banks and their respective registers.

Driving the RTL8019AS RSTDRV pin high forces the RTL8019AS to read the contents of the external ’9346 EEPROM. Because you’ll be emulating that process, PD4 is assigned to the RTL8019AS active-high RSTDRV line and PD7 performs the data output function that normally would be done by the EEDO line of a ’9346. The EE designations are relative to the EEPROM. So, EEDO is EEPROM data out and RTL8019AS data in. Port D has the ability to be open-drain and carry alternate signals. Bit ANDing of 0x6F to the special function registers of port D ensures that PD7 and PD4 will assume the functions of normal I/O pins.

PREVIOUS • NEXT