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Issue #212 March 2008
Problem 3—Both Verilog and VHDL support the concept of compile-time adjustments to the design of a particular module, in addition to the real-time signals that pass into and out of it. What is the specific syntax in each case?
Answer 3 —VHDL uses generic parameters in addition to signal ports in the definition of an entity's interface.
entity ddr_top_wrapper is
generic (
-- number of write ports & FIFOs
NUM_WR_PORTS : integer := 2;
. . .
);
port (
-- System Clock at DDR SDRAM rate
sys_clk : in std_logic;
. . .
);
end;
Verilog uses #(parameter ...) arguments in addition to the normal signal arguments on a module.
module ddr_top_wrapper
#(parameter
// number of write ports & FIFOs
NUM_WR_PORTS = 2,
. . .
)
(
// System Clock at DDR SDRAM rate
input sys_clk,
. . .
)
. . .
endmodule
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