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Issue #210 January 2008
Problem 4—How can ground bounce affect digital inputs on the same chip?
Answer 4: The input level of a digital input is interpreted relative to a threshold level set by the circuitry of the input buffer. This threshold is usually related to the chip ground voltage, either by a fixed offset (e.g., VGND + 2.0 V), or by a proportion (e.g., VCC + VGND/2).
If the chip ground voltage bounces, then this input threshold voltage bounces as well. If the bounce is high enough, it could cause an input voltage normally considered “high” to be interpreted as “low” momentarily, as the effective threshold voltage of the chip input buffer rises briefly above the actual input voltage.
This is particularly problematic in multi-chip synchronous systems, as it is usually the system clock that drives the switching of the output pins on each chip. If the ground bounce couples back into the clock input (which may still be rising to its final value), the chip may see extra clock edges that throw its internal logic out of sync with the rest of the system.
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