UPSC4 :
A
High Performance Reciprocal Counter
Project
number DL135 - Abstract
A design
contest is always a good opportunity to try to re-invent the
wheel, but only if it is a far better wheel than the existing
ones. This project, UPSC4, is not the first universal counter
designed, but implements a really innovative design approach,
understand a really cost-effective one : UPSC4 features are
head to head with the existing high-range universal counters…
but UPSC4 is built with only 10 integrated circuits !
Yes, nothing
more than 5 small analog chips, one DAC, one ADC, one UHF prescaler
… and one new ATMEL’s FPLSIC device with its initialization
EEPROM to support not only basic frequency and period measurements
but also advanced features like automatic slew rate calculation
or gated frequency measurements, min/max or rolling averages,
with gate times as low as 250µs and up to 11 digits resolution.
Moreover the flexible architecture of the UPSC4 counter will
allow to add new features without any hardware change, thanks
to the FPSLIC device.
As shown
on this block diagram, the UPSC4 counter has two input are first
amplified, and then compared with pseudo-static
trigger levels. These trigger levels are generated by the AVR
micro-controller included within the FPLSIC chip, thanks to
a D/A converter, in order to implement a true automatic trigger
mode. The input A is compared to two different levels in
order to implement rise time/fall time measurements. The high-frequency
C input is specifically managed with a UHF prescaler
chip.
In order
for the micro-controller to define the trigger levels, the two
input signals are also connected to analog peak detectors,
fed to the AVR chip through a A/D converter. All the
input and clock signals are routed to the input multiplex section
(build within the FPLSIC’s FPGA), witch select the proper input
and clock signals depending on the measurement required. This
FPGA also integrates the independant event and time
counters required by a reciprocal counter and all the real-time
control. The AVR micro-controller manage everything else, including
display and keyboard (thanks to some port extensions built within
the FPGA).
UPSC4’s
main clock is either a standard TCXO or a high precision
OCXO. For this option a step-up PLL is used, along with a digital
triming circuitry.
This block
diagram explain why the architecture of the UPSC4 counter is
extremely flexible and will allow to support virtually
any feature without any hardware change thanks to the FPSLIC
device : All the discrete hardware are generic components like
comparators, ADC, DAC and so on, and all the "feature adding"
parts like counters are integrated in the FPSLIC FPGA or executed
by the FPSLIC micro-controller. So a new software load (FPGA+ROM,
stored in the same EEPROM) is enough to synthesize a new feature
set !
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