The MPEG layer 3 (MP3) format has become the de facto standard for storing and transmitting compressed digital audio data. The standard is highly efficient, achieving compression ratios on the order of 12 to 1 with minimal loss in perceived audio quality. This compression performance comes at a price, however: MP3 audio is complex and computationally challenging to decode.

Early popular MP3 player implementations were software-only, and required high-speed general-purpose desktop computers. More recently, hardware MP3 players are becoming increasingly and MP3 decoding capabilities are appearing in a growing range of consumer devices. In order to cope with the heavy demands of real-time MP3 decoding, these devices usually use either a fairly complex, high-speed processor, or a combination of chips, with a simple processor providing system control functions, and a separate DSP-based coprocessor performing most of the decoding work.

This project demonstrates how the Atmel FPSLIC can be used to provide a simple, low-cost, highly integrated solution for embedded MP3 decoding. The FPSLIC is capable of providing all the necessary decoding elements, including storage interface, user interface, and actual MP3 decoding on a single chip. The only external components required are a storage device and a digital to analog converter (DAC) with appropriate audio interface circuitry. The FPSLIC-based design has significant cost and power consumption advantages over alternative designs; both of which are significant considerations in the consumer markettplace.

The FPSLIC is ideal for this application, because it combines two key elements: a highly capable, peripheral-rich microcontroller (the AVR core), and an FPGA architecture that lends itself to DSP applications. The FPGA is used to implement a basic 32-bit fixed-point DSP core to act as a ‘coprocessor’ for the computationally intensive aspects of the MP3 decoding routines. The DSP is essentially an ‘idiot savant’: good at math, but very limited in other respects. It has its own internal 128 * 32-bit data memory, implemented using the FreeRAM resources in the FPGA portion of the FPSLIC. The FPGA implementation includes a transfer unit to move data between the dual-ported SRAM on the FPSLIC and the internal DSP data RAM. The dual-ported SRAM is also used to store the program code for the DSP.

At 25 MHz, the current design is capable of decoding MP3 data in real time at 128 kbps, the most common encoding rate. Higher data rates could easily be supported with some additional optimization of the code, or simply by using a higher clock rate with the forthcoming 40 MHz part.

The block diagram below illustrates the major system components. Code on the AVR reads data from an attached storage device, such as a CompactFlash card, IDE hard disk drive, or ATAPI CD-ROM drive. For the more computationally intensive parts of the decoding process, the software on the AVR invokes the transfer unit in the FPGA to set up the data for the DSP. It then invokes the DSP to perform the actual computation, and finally uses the transfer unit again to read the computed data back from the FPGA.

Once the PCM data has been decoded, it is passed to a small serial data transfer unit in the FPGA to transfer it to an off-board DAC (the two-wire serial interface on the AVR side does not support the protocol used by the DAC). Transfers are interrupt-driven, and occur in parallel with the decoding of the following block.