1st Place

Geva Patz
Brighton, MA USA

Complete Abstract

MPSLIC: A Single-chip FPSLIC MP3 decoder and player

The MP3 format has become the de facto standard for storing and transmitting compressed digital audio data. The standard is highly efficient, achieving compression ratios on the order of 12 to 1 with minimal loss in perceived audio quality. This compression performance comes at a price, however: MP3 audio is complex and computationally challenging to decode. This project demonstrates how the FPSLIC can be used to provide a simple, low-cost, highly integrated solution for embedded MP3 decoding. The FPSLIC is capable of providing all the necessary decoding elements, including storage interface, user interface, and actual MP3 decoding on a single chip. The only external components required are a storage device and a DAC with appropriate audio interface circuitry. The FPSLIC-based design has significant cost and power consumption advantages over alternative designs, both of which are significant considerations in the consumer marketplace.

2nd Place

Robert Lacoste
Chaville, France

Complete Abstract

UPSC4

A design contest is always a good opportunity to try to re-invent the wheel, but only if it’s a far better wheel than the existing ones. This project, UPSC4, is not the first universal counter designed, but implements an innovative and cost-effective design approach. UPSC4 features are head to head with the existing high-range universal counters—but UPSC4 is built with only 10 integrated circuits! Yes, nothing more than five small analog chips, one DAC, one ADC, one UHF prescaler, and one Atmel FPLSIC device with its initialization EEPROM to support basic frequency and period measurements as well as advanced features such as automatic slew rate calculation or gated frequency measurements, min/max or rolling averages, with gate times as low as 250 µs and up to 11 digits resolution. Moreover the flexible architecture of the UPSC4 counter will allow you to add new features without any hardware changes.

3rd Place

Bruce Pride
Gilsum, NH USA

Complete Abstract

Slic-Stepping Debugger

The Slic Stepping Debugger system is a bench-top device that connects to an external circuit board’s microprocessor bus. It monitors, captures, and then converts a single microprocessor bus cycle into useful engineering data. That data is then displayed to the user via the system’s integrated LCD. The system is used in conjunction with a single-stepping software debugger on a PC, which is connected to the processor’s debug port. Every time the user steps through code with the software debugger, the Slic-Stepping debugger captures the first bus cycle and displays the Address bus value, Data bus value, whether it was a read or write cycle, and how big the current transfer size was. This allows the engineer to monitor and verify basic microprocessor bus cycles during development of new hardware and software designs. Of course, there are many families of microprocessors and all have different bus protocols. The first microprocessor protocol and bus that will be interfaced to will be the 32-bit PowerPC 860 family.

3rd Place

Johan Thomas & Sven Janssens
Merchtem, Belgium

Complete Abstract

An Elleptic Curve Public-Key Cryptosystem

This entry is an implementation of an elliptic curve public-key cryptosystem on a programmable SOC. A complete hardware implementation has limited flexibility, but is ideally suited for the implementation of the underlying finite field arithmetic. A complete software implementation, on the other hand, benefits the global control, but suffers from efficiency problems concerning the finite field arithmetic. We use a standard basis representation for the field elements and projective coordinates to implement the group operation. The results concerning area are comparable with existing hardware implementations. Although no attempts have been made yet to reduce the critical path delay of the hardware part, we obtained promising results towards speed and throughput. A maximum clock frequency of 10 MHz is realized, but we feel that 200 MHz could be possible after optimization.