Whilst investigating some of the CPLD devices available the need arose to create tools that would be useful to myself and to others. I chose to create a logic analyzer that would not cost an arm and a leg but rather be affordable. To this end I’ve chosen to design an eight channel logic analyzer.

With the requirement for high speed clocking and configurable settings, the heart of the analyzer is a CPLD from Lattice semiconductor. This was chosen primarily for the in circuit programming (isp) and reprogramable logic array. These devices are extremely fast, which would result in a system that is able to sample a high speed bus. All the acquisition of the signal is achieved by hardware and thus the microcontroller is free to handle the interfacing, setup and control functions.

After reset the LPC sends a startup message to the terminal via the Max232 to the PC terminal. Following which the CPU sets up the isp. The isp takes the master oscillator 80Mhz and divides it to create the clock for the LPC. This clock also provides the main timing for the capture.

Once a trigger starts, the isp will generate all the address signals, and the write pulse for the High speed RAM. To ensure that the RAM is able to capture correctly, the device select is kept active for the entire capture. The input buffer is only enabled when the download line is LOW. If the LPC was to read the data from the RAM then the download line is set HIGH and the input buffer is made inactive.

In the read state the LPC sets the Download line HIGH. Following this the S_data line is used to provide a clock to read the data from the RAM.

A red LED is connected to the download line to indicate that a capture is in progress. Once complete the Green LED will come on to indicate completion of the capture.

The power supply is a standard 5V series regulator.

The input port that is used for the connecting the probes to the analyzer was chosen to be a DB15. This connector is configured with 8 pins on the top row, lending itself to easy changes from test to test. Creating custom connections is cheap and easy.

The operation of the analyzer is as follows:

The microcontroller will setup the trigger state that needs to be met to start the acquisition of the data at the sample period.

This data is loaded into the control chip serially and upon completion the microcontroller will release the S_Rst line to arm the chip. Following this, the value on the data bus is continuously compared with the desired trigger state, until a match takes place. This will set the triggered bit and the counter will count the addresses at the selected clock rate. This trigger will indicate to the microcontroller, level on busy line, that an acquire is taking place. The data from the bus is written into the RAM until all samples are received. Upon completion this line will go high and cause an interrupt on the microcontroller to signal acquire completed.

Once the data is captured the microcontroller will assert the download line and then use the S_data line as a clock source to get the captured data. This method minimizes the number of pins required and a really compact device can be built.

The isp is able to operate at the High frequencies that are required for sampling data busses of modern microcontrollers.

Building a prototype, in SMD, in the garage on a two layer PCB resulted in an exciting challenge. Vias, pasting and baking in the toaster. Finally done and tested look at these results.

Using the analyzer is simple. Plug the DB9 connector to a terminal on any PC. Set the emulation to 19200, 1, 8, n. Power up the pocket analyzer. A boot message should be displayed on the screen.

By using the DB15 connector connect probes to the analyzer. These are to be used to monitor the desired signals.