FPGA on a Rope
The "FPGA on a Rope" board and device driver provide a simple method to
quickly configure and control a user definable FPGA connected to a Windows
98 P.C. through a USB port.
The design consists of the USBFPGA hardware (printed circuit board), and a
Windows 98 compatible WDM device driver (USBFPGA.Sys).
A download application is included (USBFPGA.Exe) which provides an interface
for downloading the users FPGA definition files.
An example application and FPGA template design are included to demonstrate
the control and status functions of the USBFPGA device. These functions
allow the user to develop custom applications that communicate with their
defined FPGA hardware via the USB port.
Components
The heart of the circuit is a Philips 87LPC764 micro-controller. This
component is an 8051 derivative featuring 4KB of one-time programmable ROM,
128 bytes of RAM, and an assortment of on-chip resources (timers, UART, I2C,
reset, etc.). All of the above features are shoe-horned into a 20 pin
package. Because the part implements an 8051 core, a wide variety of
development tools are available. The Philips 87LPC764 micro-controller has
a wide operating voltage range (2.7V to 6V) which allows it to operate from
Vusb (note: Section 7.2.2 of the USB specification shows this voltage can be
as low as 4.375V), far below the minimum voltage required by many 5V parts.
Initialization
At power up, the micro-controller initializes the USB and I2C interfaces.
The processor is clocked by the PRGCLK (programmable clock) signal which is
output from the PDIUSBD11. This signal is derived from a 48Mhz clock passed
through a programmable divider and defaults to 4Mhz at power up. The divide
value for the clock is changed from the default of 12 (48Mhz/12 = 4Mhz) to 3
(48Mhz/3 = 16Mhz) effectively shifting the processor into high gear.
Enumeration
After initialization, the firmware enters a forever loop where it waits for
events to occur. The first event (actually a whole series of events) to
occur is USB enumeration.
The USB bus is designed to be plug-and-play compatible, requiring a method
for detecting and initializing new devices, this method is called
"enumeration".
Operation
After enumeration, the device is ready to perform it's intended function as
an FPGA development platform.
The firmware, device driver, and download utility all work together to
provide the ability to configure the FPGA with the users definition file.
The user simply selects the desired definition file from within the download
utility, and the FPGA is loaded (configured) via the USB connection. The
download utility also provides for the FPGA definition file to be stored in
the EEPROM on board the USBFPGA for automatic configuration of the FPGA at
power-up. This gives the USBFPGA the ability to operate when detached from
the USB cable.
If the user implemented the USBFPGA control functions in the FPGA definition,
then the USBFPGA can be used in it's secondary function (after configuration)
as a control interface to the defined FPGA. The device driver provides
support for calls to Read and Write registers which exist in the defined FPGA,
providing an application specific control interface to the users defined FPGA
function.
Access to the user defined I/O pins of the FPGA is provided via a fifty pin
header.