This project, DDSGEN, is a full-featured high end DDS based low cost generator, able to generate sinus and square signals from 0 to 120MHz with a resolution up to 0.001Hz. DDSGEN supports a blazing list of modulation modes (AM, FM, PM, shaped keying, FSK, PSK) as well as wobbulation; It can also be extended by daughter boards to implement a full-featured ARB (Arbitrary Signal Generator) and Pulse generator. And last but not least its cost is very reasonable for such a high-end device.

DDSGEN is mainly built around an AD9852 DDS chip from Analog Devices, controlled by a pair of low cost Philips 87LPC764 micro-controllers (one main, one dedicated to the user interface).

• Autonomous device, on-board user interface (2x16 LCD, keyboard, rotary encoder) ;

• All functions can be remotely controlled through a RS232 connection ;
• 300 MHz internal clock frequency, standard 100ppm stability or OVCXO based 3ppm option :
• 0 to 120MHz output frequency with 0.001Hz resolution from 0 to 999KHz and 1Hz resolution from 1MHz to 120MHz ;
• Sinus output from 0 to +/-3V, 12 bits resolution, programmable offset 0-3V ;
• Low jitter square wave output, 3.3V/5V compatible ;
• Fully digital AM, FM, PM (Amplitude, Frequency and Phase Modulation) up to 5KHz with programmable depth, 10 bits resolution. Internal modulation generator option ;
• Shaped keying (0 to 100% amplitude modulation based on a digital signal), with programmable slope rate ;
• Digital ramped FSK (Frequency Shift Keying) between any two frequencies. Immediate of programmable change rate ;
• Digital ramped PSK (Phase Shift Keying) between any two phases (resolution 12 bits). Immediate or programmable change rate ;
• Linear wobbulation between any two frequencies, programmable repetition rate.
• Future optional ARB (Arbitrary Signal Generator) : 0 to 30MHz clock with 0.001 Hertz resolution, 12 bits amplitude resolution, 1x8Kwords signal or 8x1Kwords signals. Serial download of the waveforms through the RS232 port to an on-board EEPROM ;
• Future optional Pulse generator : 10ns maximum resolution, 24 bits length register / 32 bits repetition register.

• Optional high precision 3 ppm OVCXO system clock.

DDSGEN software is mainly written in C, thanks to the very good freeware SDCC optimizing cross-compiler. The dynamic structure of the DDSGEN embedded software is a classic (but field proven) interrupt driven one :

• After initializations, a main program manages the user interface, and stores in a shared RAM buffer all parameters that need to be loaded into the DDS chip ;

• An interrupt routine, executed each time the DDS chip asks for new values (usually each 200µs), executes an A/D conversion of the external modulation input and recalculates on-the-fly the frequency and/or amplitude and/or phase if a modulation is requested, and upload the modified parameters into the DDS chip.