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Issue #205 August
2007
Handheld Multifunction Scope
by Jingxi Zhang & Yang Zhang
Start | Circuit Description | Software Developmentt | Improvements | Sources & PDF
CIRCUIT DESCRIPTION
Figure 1 is a block diagram of the system. The LM3S811’s rich on-chip peripherals and plentiful GPIO pins make it possible to build the multifunction tool with few external components. The analog components for the signal conditioning circuit and the batteries are mounted on a small PCB. The LM3S811 evaluation board and the analog PCB are stacked back-to-back on their solder sides. Figure 2 and Figure 3 show the analog signal conditioning circuit and the connection circuit to the LM3S811 evaluation board, respectively.
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| Figure 1—This is a block diagram of the multifunction oscilloscope. The LM3S811 evaluation board is in the center. The analog signal-conditioning circuit, LC meter circuit, frequency counter, and logic probe circuit were added to the system. The slide switches, the potentiometer, and the rotary encoder provide user control to the system. The visual output is the OLED display, which is connected to the microcontroller through the I2C port and the LED. The audio output is the tiny piezo speaker. The UART port provides a serial port link through the USB port to a host PC. |
Oscilloscope mode and Voltmeter mode share the same signal conditioning circuit (see Figure 4). In these modes, the LM3S811’s GPIO PD3 pin is set to a low logic level. Thus, at the channel 1 input circuit the end of the 300-kW resistor R13 connection to the GPIO PD3 is virtually grounded. This makes the two 300-kW resistors parallel to form a 150-kW resistor in the attenuation network. With the 850-kW resistor in the input end, both channels’ input impedance is 1 MW and the attenuation rate is 15%.
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| Figure 4—This is the analog signal-conditioning circuit for the oscilloscope and voltmeter. The input resistor divider attenuates the input signal to 15%. The input buffer provides an isolation to the input. The gain of the PGA is controlled by the microcontroller through the SPI port. The last stage is the voltage shifter to translate the voltage from the analog domain to the ADC input voltage range. |
The input buffers U2 and U4 are the voltage followers that isolate the programmable gain amplifier (PGA) from the input end. (The PGA has a low-input impedance.) The diode pairs at each channel input (D3 and D4, D5 and D6) provide the protection circuit to prevent over-voltage damage to the amplifiers. Switches S7 and S8 are for the DC/AC input coupling selection. When the switch is open, a 0.1-mF capacitor is used for the AC coupling (notice that the capacitor voltage tolerance is 100 V). The Linear Technology LT6912-1 is a dual-channel PGA where each amplifier gain can be independently set to ×1, ×2, ×5, ×10, ×20, ×50, and ×100 via an SPI. The charge pump (U5, a Texas Instruments TPS60403) provides the –3-V power supply for the input buffers and the PGA. The last stage in the signal conditioning circuit is a voltage shifter. Because the PGA and the input buffer are working on both positive and negative rails to accommodate the signal in negative range while the LM3S811’s ADC is working only on the positive rail, a voltage shifter is needed to shift the signal from ±1.5 V to the 0- to 3-V range. The voltage level shifter has a unit gain for the negative input while its gain for the positive input is 2. The resistor divider made by R25 and R26 brings a static 0.75 V to the positive input. When the input is 0 V the resting output voltage to the ADC converter is shifted to 1.5 V, which is in the middle of ADC working range. The negative signal moves the output toward ground while the positive signal moves the output toward the positive rail. The low-pass filters, composed of R17, C17, R23, and C18, at the output of each voltage shifter are the antialiasing filters for filtering out the frequency components higher than the Nyquist frequency.
The fast on-chip ADC captures and digitizes the buffered dual-channel analog signal. The sampling rate is controlled by an on-chip timer. Thanks to the programmable sample conversion sequence units embedded in the LM3S811, sampled data is automatically saved in the sequence unit’s FIFO. This prevents the data from being lost in case the interrupt service routine (ISR) cannot catch up with bursting interrupt events at fast sampling rates. The ADC also samples the voltage output of the potentiometer on the evaluation board. This volt value is used to control the oscilloscope trigger level as well as to adjust the frequency and the duty cycle of the pulse generator.
Voltmeter mode uses the same circuitry as Oscilloscope mode, except only channel 1 is used. The digitized signal at the ADC output is analyzed in order to discriminate between DC and AC voltages. If the signal contains both positive and negative components, the measurement is an AC voltage and the AC flag is indicated on the display. The AC voltage is rectified by software and the average value is used for the display.
Ohmmeter mode also shares the same basic signal conditioning circuit as the Oscilloscope and Voltmeter modes. However, GPIO pin PD3 in this mode is set to VCC rail. Two 300-kW resistors form a voltage divider. The measuring resistor RTEST is parallel with the low resistor of the voltage divider (see Figure 5).
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| Figure 5—Ohmmeter mode shares the same analog circuit with the oscilloscope and the voltmeter, but with a different input resistor network. One of the 300-kW resistors is now connected to VCC rail. The resistor to be tested (RTEST) is parallel with another 300-kW resistor. When the input is open, the circuit outputs the highest voltage. The smaller the tested resistor, the lower the output voltage. By calculating the captured voltage, the resistor value can be easily determined. |
When the input end is open (the measured resistance equals ¥), the voltage at the voltage divider is about 1.65 V, which will saturate the voltage shifter output to the maximum. When RTEST is connected to the input end, the voltage at the voltage divider drops as follows:
[1]
Rearranging the terms, we get:
[2]
Because:
[3]
Rearrange the terms again to get:
[4]
Because the ADC sample is proportional to VIN by a constant factor A, which relates to the gain of the PGA, we then get:
[5]
Therefore, by substituting in the actual values, we can calculate the RTEST value by sampling the ADC input.
The PGA gain changes according to the resistor value being measured to make sure the resistor is measured at its highest resolution range.
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| Figure 6—The capacitor to be tested (CTEST) is charged or discharged through the 470-W or 470-kW resistor. When the voltage runs across the GPIO input Schmitt trigger threshold, the timer is triggered, and the tick count representing the charge/discharge period is captured. The capacitance can be deduced from the charge/discharge period, which is proportional to the RC time constant. |
Capacitance Meter mode uses a very simple RC circuit connected to the on-chip timer (timer 2A) input (see Figure 6). The CTEST is charged and discharged periodically through a resistor (the resistor value determines the testing range) by turning a driving voltage on and off. The voltage on the capacitor, VC, cannot change instantly, but it is a function of time with time constant t = RC. During discharge:
[6]
while during charge:
[7]
where V0 is the capacitor at the start of discharge and VDRIVE is the driving voltage. At the time the LM3S811 changes the driving voltage, it also starts timer 2A. When the VC reaches the threshold of VIL (during discharge) or VIH (during charge) of the LM3S811 GPIO input pin, the GPIO pin state is changed. Because this pin is the input of timer 2A, which is set to Input Edge Time Capture mode, the tick count of the time period is captured and stored in a register. Based on the captured tick count, the capacitance can be easily calculated.
There are two charge/discharge resistors. One resistor is smaller (470 W) and another is 1,000 times larger (470 kW). The large resistor is used for measuring small capacitors (from few pF to about 0.1 mF). Because the larger resistor can compensate for small capacitance and make the RC time constant t larger, the timer is able to capture an adequate tick count during the charge/discharge period for calculating the capacitance value with sufficient resolution. When measuring large capacitors, a smaller resistor is used to prevent the large time constant from saturating the 16-bit timer or prolonging the measuring period. The resistors are automatically switched by the software. The system initially uses the large resistor to measure the capacitor. If the timer is not triggered within the threshold time window, the software switches to the small resistor to complete the measurement.
Inductance Meter mode uses the same principle as Capacitance Meter mode. However, the RL circuit time constant is t = L/R. Because R is the denominator, it requires a small resistor to measure a small inductor. The small resistor in the LR circuit causes a large current, which may exceed the maximal allowance of the GPIO pin. Therefore, the inductance meter is limited to large inductance measurement.
Frequency Counter mode uses the on-chip analog comparator to convert signal waveforms to square waveforms. The capacitor C3 is for AC coupling of the input. A JFET voltage follower, Q1, is used to buffer the input signal. The resistors R8 and R10 are the bias resistors for the JFET gate. The source voltage of JFET is set to about 1.7 V. The positive input of the analog comparator is connected to the on-chip programmable band-gap voltage source and the reference voltage is set to 150 mV above the JFET source voltage. So, a small input signal (greater than 150 mV) can trigger the analog comparator, generating square wave outputs. The diodes D1 and D2 are for over-voltage protection. The comparator output is connected to the Timer 2A input through the small resistor R3. The timer is set to Input Edge Time Capture mode so the tick count between the rising edges of the square wave (representing the signal cycles period) are captured and then converted to frequency measurement by the software.
Logic Probe mode is shown in Figure 7. It shares the JFET voltage follower circuit and the on-chip analog comparator with Frequency Counter mode, but with a different reference voltage for the comparator. In addition, the input is connected to another GPIO input pin (PB6). It is straightforward for logic low, logic high, and pulse detection. However, it is a little bit tricky to detect the high-impedance open-circuit condition (tristate). In order to detect the open circuit, both the analog comparator output and the pin, PB6 events are observed.
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| Figure 7—This figure shows the logic probe circuit detecting different input states. a—When the input is high-impedance or open-circuit, the comparator outputs 1 while the PB6 input is 0. b—When the input is in high logic level, both the comparator output and the PB6 input are 1. c—When the input is in low logic level or grounded, both the comparator output and the PB6 input are 0. |
Figure 7a shows high-impedance open circuit detection. Assume the JFET gate input impedance is large enough to ignore. The voltage at the PB6 digital input pad Schmitt trigger is determined solely by the voltage divider constructed by the 3-MW and 1-MW resistors (R8 and R10 in the schematics) when the input end is open. The voltage present at PB6 input is about:
[8]
which is lower than the LM3S811 input pin logic 0 threshold (maximal HIL = 1.3 V). Then, the microcontroller reads 0 from pin PB6. The output at the JFET source is about 1.7 V due to the gate-source voltage. The comparator reference voltage is set to 1.5 V, just below the JFET source voltage of 1.7 V. The comparator output is set to Inverse mode; therefore, the comparator outputs logic 1. Therefore, the software can determine the high impedance state if the PB6 input is 0 and the comparator output is 1.
When the input end is presented a logic-1 signal (3 to 5 V, the LM3S811 is 5-V tolerant), the voltage at the pin PB6 input is forced to rise to a high level. (R8 and R10 have a weak bias.) The JFET follower output also moves to a higher voltage level and the comparator output is maintained at a high level. The software can now determine the high-level logic signal if both the PB6 and comparator output are logic 1s (see Figure 7b).
If, on other hand, the logic 0 is present at input (or grounded), the voltage at pin PB6 input is forced to 0 (again due to the weak bias of R8 and R10). The JFET follower output drops to a lower voltage level (about 0.85 V). Because it is below the 1.7-V reference voltage, the analog comparator’s inverted output is logic 0. That means the software can determine the low logic signal if both the PB6 and the comparator outputs are 0 (see Figure 7c).
The PB6 interrupt is enabled on both the rising and the falling edges. When a pulse is presented to the input, the GPIO interrupt service routine is called. Then the PB6 input logic level and the analog comparator output are checked. If they are the same logic value, a pulse is detected, the on-board LED is turned on, and a beep tone is generated. The LED and the tone are not turned off until after a 500-ms delay. A software controlled time delay makes sure the visual and audio alerts can be easily noticed even for the short pulses.
Pulse Generator mode uses a PWM interface to output a stream of pulses. The PWM is set to Countdown mode. The PWM timer-load register determines the repeat frequency while the value in the timer comparator match register determines the duty cycle. The potentiometer is the user interface for setting the repeat frequency and the duty cycle. The voltage from the potentiometer is sampled by the on-chip ADC. The digitized value is used to set the PWM timer load register when the menu is in Frequency Setting mode and to set the PWM timer match register in Duty Cycle Setting mode.
Mode selection is made by two double pole 4 throw (DP4T) slide switches. We could not find the miniature DP4T slide switch during hardware construction. Instead, we used two low-profile, miniature, single-pole 4-throw (SP4T) slide switches (Copal Electronics CUS-14B) stacked up to form a DP4T switch. Six GPIO pins on the LM3S811 are used for decoding the mode selection. The mode is selected so that when switches S1 and S2 are in positions one, two, and three, the device is in Oscilloscope/Voltmeter mode, Ohmmeter mode, and Pulse Generation mode, respectively. When switches S1 and S2 are placed in position four, the mode selection is determined by switches S3 and S4. The modes at positions one, two, three, and four of switches S3 and S4 correspond to Capacitance Meter mode, Inductance Meter mode, Frequency Counter mode, and Logic Probe mode, respectively. The edge-triggered interrupt and pull-up resistor on these GPIO pins’ edges are enabled. Therefore, when the slide changes position, one of the GPIO pins is grounded and triggers the corresponding GPIO interrupt service routine. The software, after a debouncing delay (described later), terminates the previous mode and starts the new mode function.
The menu system consists of a thumbwheel rotary encoder (S5) and display menus. The rotary encoder is a quadrature encoder in which the outputs of two channels, channel A and channel B, are 90° out of phase. Between each rotating detent step, each channel outputs a complete pulse wave. Therefore, the combination of the two channels’ outputs yields four different phases in sequence in between each detent position. These outputs are coded, instead of binary, in Gray code order where only one bit alters when the phase changes. For example, the 2-bit binary code sequence is 00, 01, 10, and 11. In Gray code, the sequence is 00, 01, 11, and 10. The next state of binary code 01 is 10, both bit 0 and bit 1 states change. In contrast, the next state of Gray code 01 is 11, only bit 1 state changes. Readers interested in the rotary encoder and Gray code may refer to “Using Rotary Encoders as Input Devices” (B. Millier, Circuit Cellar 152, 2003).
The outputs of the rotary encoder, with the mechanical switch debouncing RC networks (R6, C1, R7, and C2), are connected to two GPIO pins, PB0 and PB1, on the LM3S811. Edge-triggered interrupts on the GPIO pins are enabled. When the encoder rotates, the ISR of these GPIO pins is called. By checking the bit change in the Gray code, the software can easily detect the thumbnail rotary encoder rotating direction.
The menu items are rendered in the lower half of the OLED display screen. (See Photo 2 for the display example.) The menu display, when activated, can display three items, each with no more than four characters. If the menu list is longer than three, arrows are shown on the right and left ends of the menu display to indicate that more items are available. The currently selected item is highlighted with inverted background and foreground lighting. Rotating the encoder’s thumbwheel moves to the next or previous item, depending on the direction of rotation and the menu scrolls to the left or right to show the available items if necessary.
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| Photo 2—These are samples of the OLED display. The displays in the left column (from top to bottom) include a single-channel oscilloscope trace, a dual-channel oscilloscope trace, and a menu display showing the oscilloscope trigger selection. The displays on the right (from top to bottom) are an Ohmmeter mode display, a capacitance meter display, and a Pulse Generation mode display. |
The menu is organized as a hierarchy. For example, if the thumbwheel’s rotary encoder push button or the push button at the front panel is pressed when the slide switch is in Oscilloscope/Voltmeter mode, the top-level menu is displayed where Oscilloscope or Voltmeter mode can be selected. Highlighting Oscilloscope and pressing the thumbwheel push button brings up the Oscilloscope submenu, where single and dual-channel, gain setting, time scale, or trigger method can be selected. Selecting an item and pressing the thumbwheel will move deeper down the menu hierarchy, and so on, until a leaf item is selected.
Mechanical switch debouncing is implemented in software. There are many mechanical switches, including push buttons and slide switches, used in the device. To simplify the circuit, a software debouncing mechanism is used for all switches except rotary encoder quadrature switch output. The software uses the sysTick interrupt to handle the switch debounce delay. When a switch interrupt occurs, the ISR does not execute the command immediately. Instead, the ISR gets the current sysTick count and registers a time delay for the command. The sysTick interrupt occurs at 1-ms intervals. At each sysTick interrupt, the current tick count is compared with the registered delay tick count. If the registered delay is expired, the switch condition is reexamined. Only the delayed reexamined switch result is used to control the command execution.
Power supply modification for battery operation is made on the LM3S811 evaluation board (see Figure 8). It is powered by a USB 5-V supply. A 3.3-V linear regulator converts 5 V to 3.3 V for the LM3S811 (and the analog signal conditioning PCB). In order to allow the three AAA batteries to power the circuit when it is working in Standalone mode, the power supply circuit was modified. The PCB trace to the 3.3-V voltage regulator input is carefully cut. Note that the traces to voltage regulator pin 2 and pin 6 need to be cut separately because they are connected to the 5-V source at a different location. (We had to use a fine drill bit to carefully drill the via on the board to disconnect pin 2 from the back side of the 5-V source.) These two pins are resoldered together and connected to a power switch. The power switch is used to select either the USB 5-V source or the battery to serve the system.
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| Figure 8—This is a modification of the power supply circuit for adding a battery source. You can see the power input (pin 2) and the enable input (pin 6) of the linear voltage regulator. U7 is disconnected from the 5-V source. These pins are reconnected to a switch, where either the battery or the USB 5-V source can be selected as the power source. |
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