CURRENT ISSUE

Contests

bottom corner

Feature Article



Issue #208 November 2007
Analog Techniques
iEthernet Bootcamp
Get Started with the W5100

by Fred Eady

Start | WIZnet W5100 | Build A Development Board | WIZnet W5100 Garage Code| Congratulations! | Sources & PDF

BUILD A DEVELOPMENT BOARD

Listing 2—The W5100 datasheet talks about this with pseudocode. Here’s my translation.

#define chip_base_address 	0x0000
#define RX_memory_base_address	0x6000
#define gS0_RX_BASE 	chip_base_address + RX_memory_base_address
#define gS0_RX_MASK	0x0800 - 1
#define gS1_RX_BASE	gS0_RX_BASE + (gS0_RX_MASK + 1)
#define gS1_RX_MASK	0x0800 - 1
#define gS2_RX_BASE	gS1_RX_BASE + (gS1_RX_MASK + 1)
#define gS2_RX_MASK	0x0800 - 1
#define gS3_RX_BASE	gS2_RX_BASE + (gS2_RX_MASK + 1)
#define gS3_RX_MASK	0x0800 - 1
#define TX_memory_base_address	0x4000
#define gS0_TX_BASE 	chip_base_address + RX_memory_base_address
#define gS0_TX_MASK	0x0800 - 1
#define gS1_TX_BASE	gS0_TX_BASE + (gS0_TX_MASK + 1)
#define gS1_TX_MASK	0x0800 - 1
#define gS2_TX_BASE	gS1_TX_BASE + (gS1_TX_MASK + 1)
#define gS2_TX_MASK	0x0800 - 1
#define gS3_TX_BASE	gS2_TX_BASE + (gS2_TX_MASK + 1)
#define gS3_TX_MASK	0x0800 - 1

 


bottom corner