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Issue #204 July 2007
Are You Up for 16 Bits?
A look at Microchip's Family of 16 -Bit Microcontrollers
by Jeff Bachiochi
Start | Microchip's 16-Bit Family |Eeny, Meeny, Miny, Moe | PIC24F | PIC24H | Need DSP? | dsPIC30/33 | Standard Features | Peripheral Pin Select | DSP | DMA | Jump-Start PCBs | SMPS for $750 | Think, Enter, Win | Sources & PDF
DMA
As you can see in Figure 1, the 16-bit parts with DMA have a separate (and dedicated) bus for DMA activity. The CPU communicates with conventional SRAM across the data space X-bus and to DPSRAM port 1. It talks to the peripherals across a separate peripheral data space bus (shown in light blue). The DMA controller communicates with port 2 of the DP SRAM and the DMA port of each of the DMA-ready peripherals across a dedicated DMA transfer bus (shown in dark blue). Microchip’s 16-bit architecture allows the CPU and DMA to complete the transfer of a byte or word every bus cycle across its dedicated bus.
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| Figure 1—Separate buses allow DMA transfers to occur simultaneously with CPU program execution. Many peripherals support this background operation. |
Since either the CPU or the DMA controller can respond to a peripheral-interrupt request, you must choose any peripheral interrupt to be either a CPU or a DMA request. A DMA request will be arbitrated with any other coincident requests. If the channel wins, the transfer will be completed during the next cycle. The DMA controller retrieves the source and destination addresses from the active channel’s registers (DXAxSTA, DMAxSTB, and DMAxPAD). Block transfers are also supported. When the transfer counter reaches a user-defined limit, a CPU interrupt can be initiated to signal the CPU to process the newly received data.
The CPU and DMA controller may simultaneously read or read/write to any dual-port SRAM or DMA-ready peripheral data register. The only conflict occurs when the CPU and DMA controller simultaneously write to the same address. The CPU write will win and a “DMA fault” trap exception will be initiated. If the DMA controller writes to a location during the same bus cycle when the CPU is reading it (or vice-versa), the location is read prior to the write during the cycle in question.
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