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Issue #208 November 2007
Analog Techniques
NimbleSig
A Compact DDS RF Signal Generator
by Thomas Alldread
Second Prize Luminary Micro DesignStellaris2006 Contest
Start | Design & Hardware | Assembly | Firmware | Calibration | Operating Procedure | Project Complete | Sources & PDF
FIRMWARE
The NimbleSig firmware was written within the restraints of the free, noncommercial, evaluation version of the Keil µVision IDE, which is limited to a maximum program size of 16 KB. As I write this article, the code size is about 11 KB. Thus, there is still room to add more features. However, the commercialization of the design or the expansion of the NimbleSig code beyond the 16-KB limit would require the licensing of Keil’s µVision IDE.
The LM3S811 MPU provides sufficient onboard processing power to accurately and quickly calculate the 32-bit frequency tuning words (FTWs) with 64-bit arithmetic. The high-level C code and large program memory makes the provision of a plain-language, command-prompt-style user interface easy to implement.
The NimbleSig MPU controls the output frequency of the DDS by first calculating and then sending a 32-bit binary number called the FTW to the appropriate DDS control register. The output frequency from the DDS depends on the DDS’s internal clock frequency and the value of the FTW. The FTW is calculated by the LM3S811 MPU:
FreqO is the desired output frequency and 4,294,967,296 is 232. ClkRef is the exact frequency of the reference clock, which in this case is TCXO frequency × 20 = 400,000,000 ±calibration.
The relative output level of the DDS chip is controlled by a 14-bit digital word called the amplitude scale factor (ASF). When set at 214 – 1 or 16,383 in decimal, all 14 bits are set to the one state and the full output power level is obtained from the DDS. If it is set to half the maximum value of 214 (i.e., 16,384/2 = 8,192), the carrier output voltage from the DDS is reduced to one-half the full output (–6 dB in logarithmic, relative power-level terms). Each time the number is halved, the output voltage drops by another 6 dB. NimbleSig uses the ASF register value to calibrate the output level to –10 dBm and for amplitude modulation.
In a similar manner, the phase of the output signal can be varied by up to 360° by changing the 14-bit phase offset word (POW). The POW could be varied from a modulation source to phase modulate the DDS output. Details for the full DDS register set are in the ADI datasheets. Figure 4 is a flowchart of the NimbleSig firmware initialization and the main infinite loop.
Starting from the initial reset, startup ASM code defines the stack and heap memory allocations, application interrupt vector addresses, and fault vectors. A default handler is provided for unused interrupts. Upon completion, the start-up code jumps to the entry point of the NimbleSig C firmware. Main first initializes the MPU PLL Clock mode to 50 MHz and then the various peripherals used by NimbleSig.
The general-purpose I/O (GPIO) module is enabled and pin directions are set or pin peripheral assignments are made for ports A, B, C, and D as needed for this project. UART0 is enabled for the host communications at a data rate of 115,200 bps, 8 bits, 1 stop bit, and no parity (8N1). Timer1 is initialized for triggering the ADC0 measurement of the RF level every 100 ms. ADC0 is then enabled for RF detector output-level measurement.
The SSI is initialized in the Freescale Semiconductor mode 0 format, which is compatible with the AD9859/9951 protocol. The SSI data word width is set to 8 bits. The data rate is set to 25 Mbps.
After the interrupts and external WDT are enabled in preparation for the overall operation, the initialization is completed by sending the initial control register data to the DDS via the SSI peripheral. The program then enters the main “forever loop,” where it checks the status of flags. It loops here continuously except when summoned by hardware interrupts to service the needs of the peripherals. The source listings are available on the Circuit Cellar FTP site.
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