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Issue #208 November 2007
Analog Techniques
NimbleSig
A Compact DDS RF Signal Generator
by Thomas Alldread
Second Prize Luminary Micro DesignStellaris2006 Contest
Start | Design & Hardware | Assembly | Firmware | Calibration | Operating Procedure | Project Complete | Sources & PDF
DESIGN & HARDWARE
My goal for this project was to build a compact, inexpensive, VLF-to-VHF, AM/FM/CW multimode signal generator module that could service the signal source needs of a wide variety of applications. Figure 1 is a block diagram of the hardware. Figures 2 and 3 show the circuitry details.
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| Figure 1—This is a block and level diagram of the NimbleSig design. The module is powered by a regulated 5 V. The four onboard regulators provide the voltages needed by the TCXO, divider, DDS, and MPU. The external reference injection and post power amplifier are optional. |
The RF generator engine uses either an Analog Devices AD9859 or an AD9951 DDS IC. Both chips employ an internal 400-MHz PLL clock, which enables them to generate signals up to about 175 MHz. The compatibility of the two devices gives you a price/performance choice to best match the needs of the intended application. The AD9951 can generate a cleaner output spectrum because it uses a 14-bit DAC compared to the 10-bit DAC in the AD9859. Also, the 14-bit resolution of the AD9951 provides finer output-level control over a wider dynamic range, which is usually desirable for a signal generator application. For constant output-level applications where the DDS always runs at a maximum output level, the AD9859 might be the best techno-economic choice.
The LM3S811 microcontroller uses a 32-bit ARM Cortex-3 architecture core that runs at 50 MHz, has 64 KB of program memory, and 8 KB of RAM. It also has many peripherals, including the timers, UART, ADC, and SSI blocks needed for this project. Software development for the processor family is well supported by Keil’s µVision IDE, which employs ARM’s C compiler. Luminary Micro’s low-cost (about $50) LM3S811 evaluation module (EVM) can be used for both MPU programming and firmware debugging. This makes setting up a software development workstation for Luminary Micro’s Stellaris microcontroller family easy and inexpensive.
The small FOX924B TCXO was chosen for the 20-MHz frequency reference oscillator. The temperature stability for this device is specified at ±2 ppm from –40° to 85°C, which should meet the needs of most applications. An external reference can be used for applications with more demanding frequency stability and phase noise requirements.
The FOX924B circuit provides two 20-MHz output signals, one at 1.8 VPPP and the other at 3.3 VPP. The 1.8-V signal is used to provide a clock reference for the DDS. The internal PLL of the DDS multiplies the 20-MHz clock by 20 to achieve an internal clock rate of 400 MHz. The 3.3-VPP, 20-MHz output of the FOX924B feeds a low-voltage CMOS counter IC, which divides the frequency down to 5 MHz. This 5-MHz, 3-VPP logic signal matches the clock-reference requirements of the LM3S811 for locking its internal 200-MHz PLL, which is internally divided by four to form the 50-MHz microcontroller system clock.
The FOX924B is powered by a dedicated 3.3-V low-noise regulator because noise on its TCXO power would tend to frequency modulate the reference clock, which would degrade the output’s spectral purity. For similar reasons, a separate regulator was also provided to supply the DDS chip’s analog power bus.
The proven Analog Devices AD8307 logarithmic RF power detector was chosen for the RF power level measurement device. The wonderful detector has a 0- to 500-MHz bandwidth and offers less than ±1-dB tracking error from roughly –75 to 17 dBm. Compensation for the frequency response of the AD8307, which rolls off a few decibels in the VHF band, is accomplished here within the MPU’s firmware.
The MPU sets the state of various DDS control inputs with 3.3-V logic from GPIO pins. The MPU’s SSI peripheral provides the data communications path to the DDS chip. The SSI peripheral provides a pair of 16-word internal FIFO buffers for both output and input data. The architecture gives the MPU time to efficiently pass data in parallel format to and from the independent SSI.
The communications path to the host controller is provided by the internal UART0 peripheral. The interface passes regular 3-V unipolar data directly from the microcontroller via protection circuitry to the outside world. As the 3.3-V powered LM3S811 has 5-V tolerant I/O pins, the data ports may be directly connected to either 3- or 5-V logic external devices. Design details for my RS-232C adapter, which I use to interface to my PC serial port, can be found in the NimbleSig contest file posted on the Circuit Cellar web site (www.circuitcellar.com/designstellaris2006/winners/1648.html). SMB coaxial connectors similar to the type used for the RF ports are also used for the UART, TXD, and RXD data. Coaxial connections for the data provide shielding for any potential EMI egress or ingress from or to the RF tight NimbleSig cast aluminum enclosure.
Programming and debugging the MPU is accomplished via the JTAG port connected to the LM3S811 EVM, which in turn is connected to the development workstation PC via a USB port. The EVM connection to the NimbleSig module uses a custom-made ribbon cable that adapts the JTAG standard 20-pin header to the eight-pin, lower-profile SIP socket used here. The design for this rather simple cable is also described in the contest entry.
As you can see in Figure 1, the DDS chip’s output is fed into a 180-MHz low-pass filter, which blocks the 400-MHz clock and the sideband images that are always present in the raw output from a DDS DAC. For example, in the case of generating a 175-MHz signal, there would also be images present at 225 MHz (i.e., 400 – 175) and at 575 MHz (i.e., 400 + 175). The 13-pole elliptic filter design used here has a sufficiently sharp cut-off response to pass 175 MHz and reject frequencies above 225 MHz.
The filter was designed with two excellent freeware filter CAD programs. SVCfilter by Tonne Software was initially used to design a three-section, 180-MHz elliptic LPF. The fourth section was then added and optimized with Linear Technology’s LTspice/SwCAD III program. It found that it was possible to use 39-nH coils for each of the four inductors, which simplifies parts procurement.
The graph of the filter response that was plotted by the LTspice/SwCAD III is posted on the Circuit Cellar FTP site. The cut-off is quite sharp with the first null in the reject band around 230 MHz. The attenuation at 225 MHz is about –55 dB relative to the insertion loss at 175 MHz. Thus, the 225-MHz image (i.e., 400 – 175) is well attenuated even with the DDS operating at the maximum intended frequency limit of 175 MHz.
The minuscule, surface-mount component size 0603, 39-nH inductors (made by Murata Manufacturing) used here within the filter circuit have a minimum Q specification of 40 near the 180-MHz cutoff frequency. The Q increases to about 90 at 1 GHz with self resonance at 2.8 GHz. These characteristics make the inductors a good choice for this application.
The LPF corner frequencies of the two filters I built varied due to component tolerances. One filter limited the flattened (–10 dBm) output range to 174 MHz while the second extended it to 178 MHz.
The output from the low-pass filter may be connected directly to the output connector to provide a maximum output level of about –5 dBm or the signal can be boosted by an optional 18-dB amplifier. The optional amplifier can provide additional output power for driving passive mixers, which typically need 7-dBm local oscillator drive levels. However, for applications that require a clean spectrum, the amplifier is not a desirable option because the harmonics it generates significantly degrade the relatively clean spectrum from the DDS.
The NimbleSig module is designed to be powered from an externally regulated 5-VDC power supply. The externally regulated 5-V bus is used directly to power the AD8037 logarithmic power detector and the optional MMIC amplifier.
Thanks to Analog Devices’s low-voltage design of its DDS cores, the NimbleSig ICs do not dissipate much power. A ground tab centered under the DDS chip provides adequate heat conduction as well as a good ground connection to the PCB’s analog ground plane. The DDS chip runs barely warm to the touch.
Specific DDS chip datasheets for the ICs employed here
and various associated application notes on DDS-related topics are available
in the RF/IF components section of the Analog Devices web site. A more
detailed component-level description of the NimbleSig’s circuitry is available
on the Circuit Cellar FTP site.
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