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Issue #214 May 2008
Where Analog And Digital Collide
An Easy-To-Use LCR Meter
Third Place Microchip 2007 Design Contest
by Miguel Rusch
Start | LCR Meter | Back to Basics | The Big Picture | Creating a Wave | Analog Stages | Signal Conditioning | User Interface | Firmware | Take a Measurement | System Performance | Further Development | What's Next? | Sources & PDF
ANALOG STAGES
For this project to be effective, I had to get heavily involved in the black art of analog design. The nature of this device requires high accuracy and low noise amplification over a wide range of gains. Because considerable amplification is required for devices at either extreme of the impedance spectrum, input offset and other errors can easily saturate op-amp outputs. With this in mind, the bipolar sections of the analog circuit were handled via Analog Devices AD8629 zero-drift op-amps whose 1-µV offset and 0.002-µV/°C drift are orders of magnitude below the expected signal range.
The task of the first analog stage is to condition the test signal. The signal from the DDS chip is approximately 0.3 VPP, and its common mode voltage (CMV) is approximately 0.3 V. The signal is fed through a single-order, low-pass RC filter to further isolate clock noise. From there, it is directed to the inverting input of an AD8629 op-amp. The op-amp is configured to generate a nominal 1-VPP signal with 0-V CMV. The required offset is achieved via a voltage present on the non-inverting input that is adjusted by the MCP41010 10-kW digital potentiometer.
The resultant signal from the first stage is fed via a 1-kW 0.1% source resistor to the DUT. A four-wire Kelvin clip test lead is used to minimize the effects of the lead resistance. The test signal passes through the DUT and into the inverting input of a ground-referenced AD8629 op-amp. The current flowing through the device is then imposed as a voltage across the 1-kW 0.1% feedback resistor.
The differential signals for voltage and current are directed to separate differential instrumentation-style amplifiers constructed of three AD8629 op-amp sections each. The gain for this stage is selectable via a Vishay Intertechnology DG418L analog switch, resulting in either G = 2 or G = 128. The final op-amp in this differential configuration is referenced at 2.5 V—provided by a Microchip Technology MCP1525 precision voltage reference and buffered by a Microchip Technology MCP6022 op-amp—to minimize source impedance.
The op-amp stages need lead compensation by way of a small-capacitance (47 pF paralleled with the feedback resistor). This was necessary to ensure stability, especially for stages with minimal gain. The capacitor value was carefully chosen to not attenuate the test frequency.
The previous stage output is centered on 2.5 V but still requires additional gain for impedances greater or smaller than the source resistance. The signal is amplified in binary steps (e.g., 2, 4, 8, 16, and 32) by a Microchip MCP6S91 SPI PGA. The reference pin for this op-amp is tied to the same 2.5-V reference voltage as the previous stage.
The non-ideal realization of the design is caused by the high-frequency impedance of the DG418L analog switch, a quantity not covered in the specification sheet. At 10 kHz, the switch displays approximately 3-dB attenuation and also introduces additional phase shift. Both have to be compensated for. A more suitable component with a higher cut-off frequency will be substituted in future revisions.
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