CURRENT ISSUE Contests
Feature Article
|
|
Issue #209 December 2007
THE DARKER SIDE
Are You Locked?
A PLL Primer
by Robert Lacoste
Start | VCO Basics | PLL Basics | Integer or Fractional? | PLL Design | Silicon Trends | It's Your Turn! | Sources & PDF
PLL DESIGN
In summary, the engineering rule is quite simple. If you need to generate several frequencies spaced by a constant, a reasonably large frequency step (as compared to the inverse of the wanted lock time), and if you don’t have stringent noise requirements, then integer-N PLLs will help. Just set the PFD frequency equal to the desired frequency step size and start with a low-pass loop filter with a cutoff frequency ten times lower.
However, if you need a fine frequency resolution or have stringent phase-noise requirements, then fractional-N solutions could be a better answer. However, be ready to accept some spurious frequencies on the output spectrum and spend a little more time tweaking their setting registers. The best performances with a fractional-N PLL are often achieved with a high PFD frequency because the setting will minimize lock time and PFD noise. But that isn’t always the case. As with the integer-N PLLs, the low-pass filter should usually be set around one-tenth of the PFD frequency.
This first approach will give you a good starting point for your design. However, a more detailed analysis is needed to verify that the design works and to optimize the PLL parameters and loop filter to get the best performance. Fortunately, the main PLL chip suppliers have developed free simulation tools that make this exercise a pleasure. An example is shown in Photo 1 with Analog Devices’s ADIsimPLL tool suite, which is available on its web site. Such a tool enables you to define the system level specification of your desired PLL like minimum and maximum frequencies, channel spacing, reference frequency, and more. It then automatically proposes adequate chips (of course from the manufacturer who has offered you the tool) and compatible external VCOs if needed. After you select a loop filter and a couple of other parameters, your PC shows you the schematics for your PLL subsystem and the full simulation results both in time domain (lock time) and frequency domain (phase noise).
|
| Photo 1—This screenshot shows you how pretty PLL design tools like ADIsimPLL (Analog Devices) can be. From top to bottom: full PLL schematics calculated by the tool, a frequency-domain simulation, and a time-domain simulation. |
I must be honest with you. You may dislike the simulation result. That’s life. But you can go back and change parameters like PFD frequency or loop filter bandwidth until you are fully satisfied. The good news is in the next step: such simulations are accurate, so you shouldn’t encounter too many surprises when you switch on your soldering iron, at least if your PCB is well designed. Remember that millivolts of noise on the VCO input could generate visible phase noise or spurious signals on the output.
